Standard: IEEE 1149.7
REDUCED-PIN AND ENHANCED-FUNCTIONALITY TEST ACCESS PORT AND BOUNDARY-SCAN ARCHITECTURE
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The standard will define a link between IEEE 1149.1 interfaces in Debug and Test Systems (DTS) and IEEE 1149.1 (JTAG) interfaces in Target Systems (TS). The link defined by this standard introduces an additional layer between these legacy interfaces. This layer may be viewed as an adapter that provides new functionality and features while preserving all elements of the original IEEE 1149.1 (JTAG) interfaces. The standard will define the link behavior (including timing characteristics of signals), protocols, and functionality of the adapters deployed within the DTS and TS. The standard will not modify or create inconsistencies with IEEE 1149.1 (JTAG). The standard will define a superset of the IEEE 1149.1 specification and achieve compliance with IEEE Std 1149.1TM-2001.1
The purpose of the standard is to define a debug and test interface that meets an expanding set of challenges facing Debug and Test Systems (many of which have emerged since the inception of the original IEEE Std 1149.1) while preserving the hardware and software investments of the many industries currently using IEEE Std 1149.1-2001.
1 Information on references can be found in Clause 2.
|Organization:||The Institute of Electrical and Electronics Engineers, Inc.|
|Document Number:||ieee 1149.7|
|Most Recent Revision:||YES|
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