Standard: IEEE 1149.1

TEST ACCESS PORT AND BOUNDARY-SCAN ARCHITECTURE

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Scope:

This standard defines test logic that can be included in an integrated circuit to provide standardized approaches to:

- Testing the interconnections between integrated circuits once they have been assembled onto a printed circuit board or other substrate

- Testing the integrated circuit itself

- Observing or modifying circuit activity during the component's normal operation

The test logic consists of a boundary-scan register and other building blocks and is accessed through a test access port (TAP).

NASA Lessons:
  • Refer to Lessons Learned for Relevance to This Standard.
Organization: The Institute of Electrical and Electronics Engineers, Inc.
Document Number: ieee 1149.1
Publish Date: 2013-02-06
Page Count: 208
Change Type: COMPLETE REVISION
Available Languages: EN
DOD Adopted: NO
ANSI Approved: YES
Most Recent Revision: YES
Current Version: YES
Status: Active

Document History

Document # Change Type Update Date Revision Status
IEEE 1149.1 Change Type: REAF Revision: 01 Status: INAC
IEEE 1149.1 Change Type: STCH Update Date: 2001-06-14 Revision: 01 Status: INAC
IEEE 1149.1 Change Type: ERTA Revision: 90 Status: INAC
IEEE 1149.1 Change Type: ERTA Update Date: 1996-08-19 Revision: 90 Status: INAC
IEEE 1149.1 Change Type: Update Date: 1994-01-01 Revision: 90 Status: INAC
IEEE 1149.1 Change Type: A Update Date: 1990-05-21 Revision: 90 Status: INAC
IEEE 1149.1 Change Type: ERTA Revision: 89 Status: INAC
IEEE 1149.1 Change Type: Revision: 89 Status: INAC
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This Standard References

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