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WILEY - ESD DESIGN AND SYNTHESIS - ESD: DESIGN AND SYNTHESIS Organization: WILEY
Date: 2011-01-01
Description: Look inside for extensive coverage on: integration of cores, power bussing, and signal pins in DRAM, SRAM, CMOS image processing chips, microprocessors, analog products, RF components and how the integration influences ESD design and integration architecturing of mixed voltage, mixed signal, to RF design for ESD analysis floorplanning for peripheral and core I/O designs, and the implications on ESD and latchup guard ring integration for both a bottom-up' and top-down' methodology addressing I/O guard rings, ESD guard rings, I/O to I/O, and I/O to core classification of ESD power clamps and ESD signal pin circuitry, and how to make the correct choice for a given semiconductor chip examples of ESD design for the state-of-the-art technologies discussed, including CMOS, BiCMOS, silicon on insulator (SOI), bipolar technology, high voltage CMOS (HVCMOS), RF CMOS, and smart power practical methods for the understanding of ESD circuit power distribution, ground rule development, internal bus distribution, current path analysis, quality metrics ESD: Design and Synthesis is a continuation of the author's series of books on ESD protection.
WILEY - ESD: CIRCUITS AND DEVICES - ESD: CIRCUITS AND DEVICES - 2ND EDITION Organization: WILEY
Date: 2015-06-01
Description: • Improved coverage of low-capacitance ESD, scaling of devices and oxide scaling challenges. ESD: Circuits and Devices 2nd Edition is an essential reference to ESD, circuit & semiconductor engineers and quality, reliability &analysis engineers.
WILEY - ESD PHYSICS AND DEVICES - ESD PHYSICS AND DEVICES Organization: WILEY
Date: 2005-01-01
Description: In the continued quest to obtain a better understanding of Electrostatic Discharge (ESD), this book aims to provide a clear insight into how changes in semiconductor technology over the last 15 years have influenced the ESD robustness of semiconductor components. ESD Physics and Devices offers an accessible introduction to the subject covering thermal, mechanical and electrostatic phenomena as well as the techniques from physics and mathematics that are useful for electro-thermal and failure physics.
NASA GPR 8730.6 - ELECTROSTATIC DISCHARGE (ESD) CONTROL Organization: NASA
Date: 2006-01-05
Description: PURPOSEThis document establishes a GSFC Electrostatic Discharge (ESD) control program that complies with ANSI/ESD S20.20-1999.APPLICABILITYThis GPR applies to all organizations within the Goddard Space Flight Center (GSFC) where electronic components for flight applications, including engineering and test models and Ground Support Systems are tested, assembled, inspected, stored, or otherwise processed.
IEEE C62.47 - GUIDE ON ELECTROSTATIC DISCHARGE (ESD): CHARACTERIZATION OF THE ESD ENVIRONMENT Organization: IEEE
Date: 1992-03-19
Description: This guide organizes existing data on the subject of ESD in order to characterize the ESD surge environment. This guide is not an ESD test standard.
WILEY - ESD: RF TECHNOLOGY AND CI - ESD: RF TECHNOLOGY AND CIRCUITS Organization: WILEY
Date: 2006-01-01
Description: This enables the development of ESD design methods for RF technology, leading to increased protection against electrical overstress (EOS) and ESD. ESD: RF Technology and Circuits: Presents methods for co-synthesizisng ESD networks for RF applications to achieve improved performance and ESD protection of semiconductor chips; discusses RF ESD design methods of capacitance load transformation, matching network co-synthesis, capacitance shunts, inductive shunts, impedance isolation, load cancellation methods, distributed loads, emitter degeneration, buffering and ballasting; examines ESD protection and design of active and passive elements in RF complementary metal-oxide-semiconductor (CMOS), RF laterally-diffused metal oxide semiconductor (LDMOS), RF BiCMOS Silicon Germanium (SiGe), RF BiCMOS Silicon Germanium Carbon (SiGeC), and Gallim Arsenide technology; gives information on RF ESD testing methodologies, RF degradation effects, and failure mechanisms for devices, circuits and systems; highlights RF ESD mixed-signal design integration of digital, analog and RF circuitry; sets out examples of RF ESD design computer aided design methodologies; covers state-of-the-art RF ESD input circuits, as well as voltage-triggered to RC-triggered ESD power clamps networks in RF technologies, as well as off-chip protection concepts.
WILEY - ESD IN SILICON INTEGRATED - ESD IN SILICON INTEGRATED CIRCUITS Organization: WILEY
Date: 2002-01-01
Description: This unique reference provides the means to design protection circuits for a variety of applications and to diagnose and solve ESD problems in IC products. The coverage of state-of-the-art circuit design for ESD prevention will appeal to engineers and scientists working in the fields of IC and transistor design.
ESD - ESD TR18.0-01 - ESD ELECTRONIC DESIGN AUTOMATION CHECKS Organization: ESD
Date: 2014-01-01
Description: PURPOSE The purpose of this document is to provide a guideline for both EDA industry and ESD design community to establish a comprehensive ESD electronic design automation (EDA) verification flow satisfying the ESD design challenges of modern ICs.
NPFC - MIL-PRF-87893 - WORKSTATION, ELECTROSTATIC DISCHARGE (ESD) CONTROL Organization: NPFC
Date: 1997-01-15
Description: This specification covers electrical and construction requirements for ESD control workstations and components for use in applications where the protection of ESD sensitive (ESDS) items is required.
JEDEC JEP 157 - RECOMMENDED ESD-CDM TARGET LEVELS Organization: JEDEC
Date: 2009-10-01
Description: This document was written with the intent to provide information for quality organizations in both semiconductor companies and their customers to assess and make decisions on safe ESD CDM level requirements.
WILEY - ESD: FAILURE MECHANISMS A - ESD: FAILURE MECHANISMS AND MODELS Organization: WILEY
Date: 2009-01-01
Description: Look inside for extensive coverage on: failure analysis tools, EOS and ESD failure sources and failure models of semiconductor technology, and how to use failure analysis to design more robust semiconductor components and systems; electro-thermal models and technologies; the state-of-the-art technologies discussed include CMOS, BiCMOS, silicon on insulator (SOI), bipolar technology, high voltage CMOS (HVCMOS), RF CMOS, smart power, gallium arsenide (GaAs), gallium nitride (GaN), magneto-resistive (MR) , giant magneto-resistors (GMR),  tunneling magneto-resistor (TMR),  devices; micro electro-mechanical (MEM) systems, and  photo-masks and reticles; practical methods to use failure analysis for the understanding of ESD circuit operation, temperature analysis, power distribution, ground rule development, internal bus distribution, current path analysis, quality metrics, (connecting the theoretical to the practical analysis); the failure of each key element of a technology from passives, active elements to the circuit, sub-system to package, illusterated with case studies of the elements, circuits and system-on-chip (SOC) in todays products. ESD: Failure Mechanisms and Models is a continuation of the authors series of books on ESD protection.
NPFC - QPL-87893 - WORKSTATION, ELECTROSTATIC DISCHARGE (ESD) CONTROL Organization: NPFC
Date: 2017-02-15
Description: QUALIFIED PRODUCT LIST OF PRODUCTS QUALIFIED UNDER PERFORMANCE SPECIFICATION MIL-PRF-87893 WORKSTATION, ELECTROSTATIC DISCHARGE (ESD) CONTROL This QPL has been prepared for use by or for the government in the acquisition of products covered by the subject specification, and inclusion of a product is not intended to and does not connote endorsement of the product by the Department of Defense.
NPFC - DI-RELI-80669 - ELECTROSTATIC DISCHARGE (ESD) CONTROL PROGRAM PLAN Organization: NPFC
Date: 1992-08-28
Description: PURPOSE This plan describes the contreactor's electrostatic discharge (ESD) control program, and the controls and monitoring provisions leveled on subcontractors and suppliers to establish, implement, document, and monitor the ESD control program.
ESD - ANSI/ESD S541 - PACKAGING MATERIALS FOR ESD SENSITIVE ITEMS Organization: ESD
Date: 2008-01-01
Description: This document does not address protection from EMI/RFI/EMP or protection of volatile materials. ESD protective packaging is a requirement of the overall ESD control program ANSI/ESD S20.20. PURPOSE This standard defines the packaging properties needed to protect electrostatic discharge susceptible (ESDS) electronic items through all phases of production, transport and storage.
SAE J551-15 - VEHICLE ELECTROMAGNETIC IMMUNITY - ELECTROSTATIC DISCHARGE (ESD) Organization: SAE
Date: 2015-09-01
Description: This SAE Standard specifies the ESD test methods and procedures necessary to evaluate electronic modules intended for vehicle use.
NASA-LLIS-0777 - LESSONS LEARNED - ELECTROSTATIC DISCHARGE (ESD) TEST PRACTICES Organization: NASA
Date: 2000-04-13
Description: Practice: Test satellites for the ability to survive the effects of electrostatic discharges (ESDs) caused by a space charging environment. Such environments include Earth equatorial orbits above 8000 km and virtually all orbits above 40 degrees latitude, Jupiter encounters closer than 15 Rj (Jupiter radii), and possibly other planets.
IEEE C62.38 - GUIDE ON ELECTROSTATIC DISCHARGE (ESD): ESD WITHSTAND CAPABILITY EVALUATION METHODS (FOR ELECTRONIC EQUIPMENT SUBASSEMBLIES) Organization: IEEE
Date: 1994-10-24
Description: Also, this guide does not specify tests for completed equipment or systems, whether powered or not, nor does it specify ESD tests for individual electronic components, such as integrated circuits. Such ESD tests are covered in other standards (see IEC Pub 801-2 (1991), [B1], 1 [B2], and [B4]).
ESD - ESD TR22.0-01 - RELEVANT ESD FOUNDRY PARAMETERS FOR SEAMLESS ESD DESIGN AND VERIFICATION FLOW Organization: ESD
Date: 2014-01-01
Description: The purpose is to ensure seamless design integration and ESD EDA verification of IC level ESD concepts [1, 2]. Partial information e.g. on HBM robustness of certain ESD structures or even IO cells, is not sufficient to guarantee a successful IC level ESD concept.
JEDEC JEP 162 - SYSTEM LEVEL ESD PART II: IMPLEMENTATION OF EFFECTIVE ESD ROBUST DESIGNS Organization: JEDEC
Date: 2013-01-01
Description: This white paper consolidates industry-wide knowledge and experience on the tools and methods used to address failures of printed circuit boards (PCBs) which occur as a result of IEC 61000-4-2 system-level ESD stressing. These include both hard and soft failures, but more emphasis is placed on soft failures from all the observed and anticipated failures and failure scenarios.
NASA-LLIS-0732 - LESSONS LEARNED – ELECTROSTATIC DISCHARGE (ESD) CONTROL IN FLIGHT HARDWARE Organization: NASA
Date: 2000-04-03
Description: Practice: Apply an Electrostatic Discharge (ESD) Control Program to all spaceflight projects to ensure that ESD susceptible hardware is protected from damage due to ESD.

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