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DOD - DESC-DWG-85015 - MICROCIRCUITS, DIGITAL CMOS SERIAL CONTROLLER INTERFACE MONOLITHIC SILICON Organization: DOD
Date: 1987-04-17
Description: The complete part number shall be as shown in the following example: The device type shall identify the circuit function as follows: Device type Generic number Frequency Circuit 01 82C52 16 MHz CMOS monolithic serial controller interface The case outlines shall be as designated in appendix C of MIL-M-38510, and as follows: Outline letter Case outline X D-10 (28-lead, ½" × 1 ⅜"), dual-in-line package 3 C-4 (28-terminal, .450" × .450"), square chip carrier package Supply voltage (referenced to ground) - - - - - - - - - - +8.0 V dc Input, output, or I/O, voltage applied- - - - - - - - - - GND −0.5 V dc to VCC +0.5 V dc Storage temperature range - - - - - - - - - - - - - - - - −65°C to +150°C Maximum power dissipation (PD)- - - - - - - - - - - - - - 1 watt Lead temperature (soldering 10 seconds) - - - - - - - - - +260°C Maximum junction temperature (TJ) - - - - - - - - - - - - +150°C Thermal resistance, junction-to-case (ΘJC): Case X- - - - - - - - - - - - - - - - - - - - - - - - - 18°C/W Case 3- - - - - - - - - - - - - - - - - - - - - - - - - 60°C/W 1/ Supply voltage (VCC)- - - - - - - - - - - - - - - - - - - 4.5 V dc minimum to 5.5 V dc maximum Frequency of operation - - - - - - - - - - - - - - - - - 16 MHz maximum Case operating temperature range (TC) - - - - - - - - - - −55°C to +125°C Operating supply current (ICCOP) (outputs open) - - - - - 3.0 mA maximum 2/ Read disable (tRHDZ) - - - - - - - - - - - - - - - - - - 0 to 60 ns maximum 3/ IX input rise or fall time (tr, tf) - - - - - - - - - - - tx 4/
JEDEC JESD 82-22 - INSTRUMENTATION CHIP DATA SHEET FOR FBDIMM DIAGNOSTIC SENSELINES Organization: JEDEC
Date: 2006-11-01
Description: A counter is used to determine the VCO frequency. The device has a serial I2C data interface. The device is available in a 28 pin TQFN package and is specified over the extended industrial (-40 C to +85 C) temperature range.
IEEE 1596 - STANDARD FOR SCALABLE COHERENT INTERFACE (SCI) - IEEE COMPUTER SOCIETY DOCUMENT Organization: IEEE
Date: 1992-03-19
Description: This link is able to transfer the 17th bit that makes possible a transparent synchronous interface with the parallel 16-bit-plus-flag SCI link. The other serial links considered needed occasional extra symbols in place of the flag bit, which made such an interface much more difficult because the serial and parallel clock frequencies could not have a constant ratio.
IEEE 1212.1 - STANDARD FOR COMMUNICATING AMONG PROCESSORS AND PERIPHERALS USING SHARED MEMORY (DIRECT MEMORY ACCESS - DMA) - IEEE COMPUTER SOCIETY DOCUMENT Organization: IEEE
Date: 1993-06-17
Description: Scope of DMA recommendationsThis document describes a DMA Framework that provides recommended architectures for high-performance interfaces between Functions1 and System Memory, connected by buses that are generally compatible with the IEEE Std 1212-1991 CSR Architecture,2 such as Futurebus+ [B1] , [B2] and Serial Bus [B4] .3 These buses are characterized by high bandwidth, but have significant delays compared to Processor access to cache, particularly when used to interconnect multiple buses or large numbers of mostly independent units.

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