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IPC-TM-650 2.5.7.2

Dielectric Withstanding Voltage (Hipot Method) - Thin Dielectric Layers for Printed Boards

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Organization: IPC
Publication Date: 1 November 2009
Status: active
Page Count: 3
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The dielectric withstanding voltage test (Hipot test) consists of the application of a voltage higher than the operating voltage for a specific time across the thickness of the test specimen's dielectric layer. This is used to prove that a printed board can operate safely at its rated voltage and withstand momentary voltage spikes due to switching, surges, and other similar phenomena. Although this test is similar to a voltage breakdown test, it is not intended for this test to cause insulation breakdown. Rather, it serves to determine whether the test specimen's layers have adequate withstanding voltage. This document is applicable to thin dielectric materials such as those defined by IPC-4821. The results can be indicative of a change or a deviation from the normal material characteristics resulting from manufacturing, processing or aging conditions. The test is useful for quality acceptance and in the determination of the suitability of the material for a given application and may be adapted for process control.

Document History

IPC-TM-650 2.5.7.2
November 1, 2009
Dielectric Withstanding Voltage (Hipot Method) - Thin Dielectric Layers for Printed Boards
The dielectric withstanding voltage test (Hipot test) consists of the application of a voltage higher than the operating voltage for a specific time across the thickness of the test specimen's...
December 1, 2007
Dielectric Withstanding Voltage (HiPot Method) - Thin Dielectric Layers for Printed Circuit Boards (PCBs)
The dielectric withstanding voltage test (also called high-potential, over potential, voltage breakdown, or dielectric strength test) consists of the application of a voltage higher than rated...

References

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