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DLA - DSCC-VID-V62/18605

MICROCIRCUIT, LINEAR-DIGITAL, MICROCONTROLLER, MONOLITHIC SILICON

active, Most Current
Organization: DLA
Publication Date: 7 November 2018
Status: active
Page Count: 46
scope:

This drawing documents the general requirements of a high performance microcontroller microcircuit, with an operating temperature range of -55°C to +125°C.

Document History

DSCC-VID-V62/18605
November 7, 2018
MICROCIRCUIT, LINEAR-DIGITAL, MICROCONTROLLER, MONOLITHIC SILICON
This drawing documents the general requirements of a high performance microcontroller microcircuit, with an operating temperature range of -55°C to +125°C.

References

This document references:
JEDEC JEP 155 - Recommended ESD Target Level for HBM Qualification
Published by JEDEC on July 1, 2018
The intent of this report is to document and provide critical information to assess and make decisions on safe ESD level requirements. The scope of this document is to provide this information to...
This document references:
JEDEC JEP 157 - Recommended ESD-CDM Target Levels
Published by JEDEC on October 1, 2009
This document was written with the intent to provide information for quality organizations in both semiconductor companies and their customers to assess and make decisions on safe ESD CDM level...
This document references:
JEP95 BOOK 1 - Book One Registered and Standard Outlines for Solid State and Related Products
Published by JEDEC on March 1, 1997
PREFACE This Publication contains those solid state product outlines and other associated drawings that have been registered and assigned a JEDEC designation and are printed on white paper. Product...
This document references:
JEDEC JESD 51-2 - Integrated Circuits Thermal Test Method Environmental Conditions - Natural Convection (Still Air)
Published by JEDEC on January 1, 2008
This document outlines the environmental conditions necessary to ensure accuracy and repeatability for a standard junction-to-ambient thermal resistance measurement in natural convection.
This document references:
JEDEC JESD 51-3 - Low Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
Published by JEDEC on August 1, 1996
This standard describes design requirements for a single layer, leaded surface mount integrated circuit package thermal test board. The standard describes board material and geometry requirements,...
This document references:
JEDEC JESD 51-7 - High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
Published by JEDEC on February 1, 1999
This fixturing further defines the environment for thermal test of packaged microelectronic devices. Its function is to provide an alternate mounting surface for the analysis of heat flow in...
This document references:
JEDEC JESD 51-9 - Test Boards for Area Array Surface Mount Package Thermal Measurements
Published by JEDEC on July 1, 2000
This standard covers the design of printed circuit boards (PCBs) used in the thermal characterization of ball grid array (BGA) and land grid array (LGA) packages. It is intended to be used in...
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