CEI - EN IEC 61189-5-501
Test methods for electrical materials, printed boards and other interconnection structures and assemblies Part 5-501: General test methods for materials and assemblies - Surface insulation resistance (SIR) testing of solder fluxes
Organization: | CEI |
Publication Date: | 1 October 2021 |
Status: | active |
Page Count: | 28 |
ICS Code (Printed circuits and boards): | 31.180 |
scope:
This part of IEC 61189 is used to quantify the deleterious effects of flux residues on surface insulation resistance (SIR) in the presence of moisture.
Interdigitated comb patterns comprising long parallel electrodes on an IPC B53 standardized test coupon are used for the evaluation. Coupons are conditioned and measurements taken at a high temperature and humidity. The electrodes are electrically biased during conditioning to facilitate electrochemical reactions, as shown in Figure 1 and Figure 3.
Reference can be made to IEC TR 61189-5-506, which examines different geometry comb patterns: 400 μm x 500 μm; 400 μm x 200 μm; and 318 μm x 318 μm.
Specifically, this method is designed to simultaneously assess:
• leakage current caused by ionized water films and electrochemical degradation of test vehicle, (corrosion, dendritic growth);
• provide metrics that can appropriately be used for binary classification (e.g. go/no go; pass/fail);
• compare, rank or characterize materials and processes.
This test is carried out at high humidity and heat conditions.