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NPFC - MIL-M-38510/250

MICROCIRCUITS, DIGITAL, CMOS, 512 X 9 BIT, FIRST IN - FIRST OUT DUAL PORT MEMORY (FIFO), MONOLITHIC SILICON

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Organization: NPFC
Publication Date: 30 October 1986
Status: active
Page Count: 25
scope:

This specification covers the detail requirements for monolithic silicon, CMOS, first in - first out dual port memory microcircuits. One product assurance class and a choice of case outlines and lead finishes are provided and are reflected in the complete part number.

The part number shall be in accordance with MIL-M-38510, and as specified herein.

The device type shall be as follows:

Device type Circuit organization Access time 01 512/9 - bit FIFO 120 ns 02 512/9 - bit FIFO 100 ns 03 512/9 - bit FIFO 80 ns

The device class shall be the product assurance level as defined in MIL-M-38510.

The case outlines shall be designated as follows:

Outline letter Case outline (see MIL-M-38510, appendix C) Y D-10 (28-lead, ½" × 1 ⅜"), dual-in-line package Z C-12 (32-terminal, .450" × .450"), leadless chip carrier

Supply voltage range (VCC) - - - - - - - - - - −0.5 V dc to +7.0 Vdc Voltage on any pin (referenced to ground)- - - −0.5 V dc to +7.0 V dc Storage temperature range- - - - - - - - - - - −65°C to +150°C Maximum power dissipation- - - - - - - - - - - 1.0W Lead temperature (soldering, 5 seconds)- - - - +270°C Maximum junction temperature (TJ) 1/ - - - - - +150°C Thermal resistance, junction-to-case (θJC): Case Y - - - - - - - - - - - - - - - - - - - °C/W Case Z - - - - - - - - - - - - - - - - - - - °C/W

Supply voltage: VCC - - - - - - - - - - - - 4.5 V dc minimum to 5.5 V dc maximum VSS - - - - - - - - - - - - GND Minimum high-level input voltage (VIH) - - - 2.0 V dc (2.4 V dc at −55°C) Minimum high-level input voltage (VIL) - - - 0.8 V dc Case operating temperature range (TC) - - - −55°C to +125°C

Beneficial comments (recommendations, additions, deletions) and any pertinent data which may be of use in improving this document should be addressed to: Rome Air Development Center (RBE-2), Griffiss AFB, NY 13441, by using the self-addressed Standardization Document Improvement Proposal (DD Form 1426) appearing at the end of this document or by letter.

intended Use:

Microcircuits conforming to this specification are intended for original equipment design application and logistic support of existing equipment.

Document History

September 8, 2020
Microcircuits, Digital, CMOS, 512 x 9 Bit, First In - First Out Dual Port Memory (FIFO), Monolithic Silicon
A description is not available for this item.
November 30, 2010
Microcircuits, Digital, CMOS, 512 x 9 Bit, First In - First Out Dual Port Memory (FIFO), Monolithic Silicon
A description is not available for this item.
February 6, 2006
MICROCIRCUITS, DIGITAL, CMOS, 512 X 9 BIT, FIRST IN - FIRST OUT DUAL PORT MEMORY (FIFO), MONOLITHIC SILICON
A description is not available for this item.
May 1, 2001
MICROCIRCUITS, DIGITAL, CMOS, 512 X 9 BIT, FIRST IN - FIRST OUT DUAL PORT MEMORY (FIFO), MONOLITHIC SILICON
A description is not available for this item.
July 24, 1995
MICROCIRCUITS, DIGITAL, CMOS, 512 X 9 BIT, FIRST IN - FIRST OUT DUAL PORT MEMORY (FIFO), MONOLITHIC SILICON
A description is not available for this item.
MIL-M-38510/250
October 30, 1986
MICROCIRCUITS, DIGITAL, CMOS, 512 X 9 BIT, FIRST IN - FIRST OUT DUAL PORT MEMORY (FIFO), MONOLITHIC SILICON
This specification covers the detail requirements for monolithic silicon, CMOS, first in - first out dual port memory microcircuits. One product assurance class and a choice of case outlines and lead...

References

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