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JEDEC JESD 52

Description of Low Voltage TTL-Compatible CMOS Logic Devices

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Organization: JEDEC
Publication Date: 1 November 1995
Status: active
Page Count: 14
scope:

This standard describes dc interface specifications and test environment for these devices that operate with 2.7 V to 3.6 V power supplies. The goal is to provide a consistent set of dc specifications for reference by logic suppliers and users alike.

Document History

JEDEC JESD 52
November 1, 1995
Description of Low Voltage TTL-Compatible CMOS Logic Devices
This standard describes dc interface specifications and test environment for these devices that operate with 2.7 V to 3.6 V power supplies. The goal is to provide a consistent set of dc...

References

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