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IEEE 61691-4

Behavioural languages - Part 4: Verilog hardware description language

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Organization: IEEE
Publication Date: 1 October 2004
Status: active
Page Count: 862
scope:

Objectives of this standard

The intent of this standard is to serve as a complete specification of the Verilog ® Hardware Description Language (HDL). This document contains

- The formal syntax and semantics of all Verilog HDL constructs

- The formal syntax and semantics of Standard Delay Format (SDF) constructs

- Simulation system tasks and functions, such as text output display commands

- Compiler directives, such as text substitution macros and simulation time scaling

- The Programming Language Interface (PLI) binding mechanism

- The formal syntax and semantics of access routines, task/function routines, and Verilog procedural interface routines

- Informative usage examples

- Informative delay model for SDF

- Listings of header files for PLI

Document History

IEEE 61691-4
October 1, 2004
Behavioural languages - Part 4: Verilog hardware description language
Objectives of this standard The intent of this standard is to serve as a complete specification of the Verilog ® Hardware Description Language (HDL). This document contains — The formal syntax and...

References

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