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JEDEC JESD 36

Standard for Description of Low-Voltage TTL-Compatible, 5 V-Tolerant CMOS Logic Devices

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Organization: JEDEC
Publication Date: 1 June 1996
Status: active
Page Count: 13
scope:

This standard outlines the standard dc specifications, test conditions, and test loading for logic products that are designed to tolerate input and output voltages which exceed the device's power supply. More specifically this standardizes 5 V - tolerant logic prducts that run from 'low voltage' (2.7 V to 3.6 V) power supplies. Products that meet this standard can be used to effectively interface between LVCMOS/LVTTL and 5 V TTL buses, bridging the gap between low-voltage and 5 V TTL busses

Document History

JEDEC JESD 36
June 1, 1996
Standard for Description of Low-Voltage TTL-Compatible, 5 V-Tolerant CMOS Logic Devices
This standard outlines the standard dc specifications, test conditions, and test loading for logic products that are designed to tolerate input and output voltages which exceed the device's power...

References

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