JEDEC JESD 247
Multi-wire Multi-level I/O Standard
|Publication Date:||1 June 2016|
This standard defines the DC and AC operating conditions, I/O impedances, termination characteristics, and compliance test methods of I/O drivers and receivers used in multi-wire, multi-level signaling interfaces. The multiwire interfaces defined by this specification all utilize quaternary signal levels.
Multi-wire signaling encodes n-bits of data per symbol onto an interface consisting of m-wires and utilizing quaternary signal levels. Differential signaling represents a simple multi-wire code where m = 2. Multi-wire signaling interfaces with m > 2 provide noise immunity and signal integrity characteristics similar to differential signals, but with higher throughput per wire.
This standard defines (1) several multi-wire signaling codes that are supported by this standard, (2) specifications for I/O drivers and receivers that support these codes, and (3) compliance test methods used to test interfaces that utilize these I/O drivers and receivers. The specifications and compliance methods in this standard are intended to be sufficient to ensure the interoperability of devices from different manufacturers. Where possible, these test methods incorporate existing techniques used by the industry to test similar devices.
This standard defines I/O drivers and receivers that are consistent with use for a minimal loss, low skew channel between two devices that are mounted immediately next to each other within a multi-chip module. Specifications that use this standard by reference will define the maximum baud rate and channel insertion loss based on the requirements of the target application. Specifications for applications which drive outside of a package to a DIMM may specify additional requirements for channel loss, channel skew, channel crosstalk, supply offset, transmit equalization, receive equalization, and skew tolerance.