UNLIMITED FREE ACCESS TO THE WORLD'S BEST IDEAS

close
Already an Engineering360 user? Log in.

This is embarrasing...

An error occurred while processing the form. Please try again in a few minutes.

Customize Your Engineering360 Experience

close
Privacy Policy

This is embarrasing...

An error occurred while processing the form. Please try again in a few minutes.

ESD TR17.0-01

ESD Process Assessment Methodologies in Electronic Production Lines – Best Practices Used in Industry

active, Most Current
Buy Now
Organization: ESD
Publication Date: 1 January 2015
Status: active
Page Count: 64
scope:

INTRODUCTION

For more than two decades, the robustness of integrated circuits (ICs) against electrostatic discharges (ESD) has been defined by two values, 2,000 volts human body model (HBM) robustness and 500 volts charged device model (CDM) robustness. It has been assumed that both of these robustness levels would provide a safe margin for handling of ICs during processing, assembly, and testing. Both values are "historic" values and have been commonly accepted, with some exceptions towards higher values for specific applications.

Rapid technology scaling and increasing demands for high-speed interfaces with very low pin capacitance are making it challenging to achieve the historic ESD target levels. It is not clear whether the historic target levels are justified by "real" ESD threats in electronic production and testing facilities. Depending on the ESD control, the target levels could be too high, resulting in over-engineering or performance constraints and, consequently, adding additional costs. It could be argued that with well-implemented static control process according to international standards such as ANSI/ESD S20.20 [1] or IEC 61340-5-1 [2], a HBM robustness of 2,000 volts exceeds the maximum possible charging of personnel by more than one order of magnitude and, therefore, the HBM robustness could be reduced. Additionally, in many cases during processing, assembly and testing, charging of devices could not be avoided and in many processes 500 volts charging can be exceeded easily - questioning whether a CDM robustness of 500 volts will really guarantee safe handling.

Considering today's commonly practiced ESD control measures and the ESD design constraints, the Industry Council on ESD Targets suggests a reduction of the HBM robustness target from 2,000 volts to 1,000 volts [3] and a reduction of the CDM robustness target from 500 volts to 250 volts [4]. It is clear that future technology nodes and high-speed applications will demand further reduction of HBM and CDM robustness.

With decreasing ESD robustness of ICs, ESD control measures during handling of ICs are becoming increasingly important and detailed process assessments will be required. In many process steps, the basic principles of ESD control measures can be assessed easily. For example, the process steps in which devices are handled manually require grounded personnel; the grounding can be verified by ESD testers combined with an access control. However, in automated tools the assessment of charging and possible discharge paths can be a difficult task.

Today, there are no standards that define the steps that are required to assess a process (step) or to finally answer the question about whether an IC with known ESD robustness can be handled safely. The ESDA working group 17.0 started to work on a "standard" document which defines the required steps. As a first step, the working group (WG) decided to compile the recent publications of the members of the WG in one technical report (TR). The goal of the TR is to give the reader examples of "best practices" of process assessment methodologies and test methods. These papers (or portions of papers) were considered state of the art at the time of publication. They have been included in this document with minimal changes. While various specifics may have changed in the intervening years, the approaches to the assessment of risk and risk mitigation remain relevant.

After a short introduction in Section 2.0 on ESD threats, models, and real-life scenarios, four different approaches of process assessments are described in Section 3.0. Those examples cover a broad range of possible threats in process steps and cite examples of appropriate measurement methodologies. Section 4.0 summarizes test methods and the work in the standardization bodies. A summary including possible flow charts for process assessments and measurement methodologies and an outlook to the next steps within the ESDA standardization WG conclude the TR.

Document History

ESD TR17.0-01
January 1, 2015
ESD Process Assessment Methodologies in Electronic Production Lines – Best Practices Used in Industry
INTRODUCTION For more than two decades, the robustness of integrated circuits (ICs) against electrostatic discharges (ESD) has been defined by two values, 2,000 volts human body model (HBM)...

References

Advertisement