JEDEC JESD 82-24
Definition of the SSTUB32865 for DDR2 RDIMM Applications 28-bit 1:2 Registered Buffer with Parity
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| Organization: | JEDEC |
| Publication Date: | 1 May 2007 |
| Status: | active |
| Page Count: | 30 |
scope:
This standard defines standard specifications of dc interface parameters, switching parameters, and test loading for definition of the SSTUB32865 registered buffer with parity for 2 rank by 4 or similar high-density DDR2 RDIMM applications. The SSTUB32865 is identical in functionality to the SSTU32865 but specifies tighter timing characteristics and a higher application frequency of up to 410MHz.
Document History
January 1, 2023
Definition of the SSTUB32865 28-bit 1:2 Registered Buffer with Parity for DDR2 RDIMM Applications
This standard defines standard specifications of DC interface parameters, switching parameters, and test loading for definition of the SSTUB32865 registered buffer with parity for 2 rank by 4 or...
JEDEC JESD 82-24
May 1, 2007
Definition of the SSTUB32865 for DDR2 RDIMM Applications 28-bit 1:2 Registered Buffer with Parity
This standard defines standard specifications of dc interface parameters, switching parameters, and test loading for definition of the SSTUB32865 registered buffer with parity for 2 rank by 4 or...
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