IEEE 1149.10

High-Speed Test Access Port and On-Chip Distribution Architecture

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Organization: IEEE
Publication Date: 18 May 2017
Status: active
Page Count: 96
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This standard defines a high speed test access port for delivery of test data, a packet format for describing the test payload, and a distribution architecture for converting the test data to/from... View More

Document History

IEEE 1149.10
May 18, 2017
High-Speed Test Access Port and On-Chip Distribution Architecture
This standard defines a high speed test access port for delivery of test data, a packet format for describing the test payload, and a distribution architecture for converting the test data to/from...

References

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