System, Software, and Hardware Verification and Validation
|Publication Date:||1 January 2016|
This verification and validation (V&V) standard is a process standard that addresses all system, software, and hardware life cycle processes including the Agreement, Organizational Project-Enabling, Project, Technical, Software Implementation, Software Support, and Software Reuse process groups. This standard is compatible with all life cycle models (e.g., system, software, and hardware); however, not all life cycle models use all of the processes listed in this standard.
V&V processes determine whether the development products of a given activity conform to the requirements of that activity and whether the product satisfies its intended use and user needs. This determination may include the analysis, evaluation, review, inspection, assessment, and testing of products and processes.
The user of this standard may invoke those life cycle processes and the associated V&V processes that apply to the project. A description of system life cycle processes may be found in ISO/IEC/IEEE 15288:2015(E) [B16], 1 and a description of software life cycle processes may be found in ISO/IEC 12207:2008 [B11]. Annex A maps ISO/IEC/IEEE 15288:2015(E) [B16] (Table A.1 and Table A.2) and ISO/IEC 12207:2008 [B11] (Table A.3 and Table A.4) to the V&V activities and tasks defined in this standard.
This standard defines the verification and validation processes that are applied to the system, software, and hardware development throughout the life cycle, including acquisition, supply, development, operations,
The purpose of this standard is to:
Establish a common framework of the V&V processes, activities, and tasks in support of all system, software, and hardware life cycle processes.
Define the V&V tasks, required inputs, and required outputs in each life cycle process.
Identify the minimum V&V tasks corresponding to a four-level integrity schema.
Define the content of the Verification and Validation Plan