NPFC - MIL-HDBK-528
DESIGN FOR TESTABILITY (DFT) FOR BOUNDARY SCAN DIAGNOSTICS (BSD)
|Publication Date:||31 October 2017|
This handbook provides guidance for the Department of Defense (DoD) to acquire avionics systems that use Boundary Scan. This document describes the design considerations necessary for a host system to implement Boundary Scan Diagnostics (BSD). Boundary Scan is a technique used to test the interconnections between integrated circuits (ICs) on a printed circuit boards (PCBs), as well as to test the health of the ICs themselves and to load data into them. Boundary Scan can also be used in a system-level configuration between several boards. Boundary Scan is low cost and requires less physical access to circuit components than traditional testing techniques, such as In-Circuit Testing (ICT) for detecting and isolating component failures. With today's highly complex and dense circuit cards, Boundary Scan is a useful technique for troubleshooting and ensuring production quality.
The Joint Test Action Group (JTAG), an electronics industry association formed in 1985, has used Boundary Scan to develop the Institute of Electrical and Electronic Engineers (IEEE) Standard 1149.1-1990, titled "Standard Test Access Port and Boundary-Scan Architecture." This IEEE standard has become synonymous and interchangeable with the group's name. Therefore, this handbook will use the terms "Boundary Scan" and "JTAG" interchangeably. Boundary Scan/JTAG can be used at various levels of maintenance for testing avionic circuit cards. DoD can benefit from this technology as it will enhance the reliability, availability, and maintainability (RAM) of avionics and, as a result, increase operational availability (Ao) and potentially reduce the total ownership cost (TOC) of systems acquired.
Boundary Scan can test the interconnections of ICs such as Field Programmable Gate Arrays (FPGAs) and Central Processing Units (CPUs) on a PCB for short and open circuit faults. Data is sent to the IC from a piece of Automatic Test Equipment (ATE), or from a Personal Computer (PC). The output of the IC is sent back to the ATE to be examined. With multiple ICs on a PCB, the ATE sends the boundary scan test signal into the first IC and the output of this IC will be the input of the next IC, the output of the second IC will be the input to the third IC, and so on. The output of the last IC on the PCB will be sent back to the ATE for examination, thus creating a chain, also known as the "scan chain." A two-IC configuration example is shown on Figure 1. The scan chain verifies that the Boundary-Scan-enable
Boundary Scan can also be used in a system-level test configuration, connecting multiple boards. Just as boundary scan can connect multiple ICs to form a scan chain, system-level boundary scan can form a chain between multiple boards, allowing testing interconnections across multiple boards using only one source. System-level boundary scan can be configured in many different topologies. Some of the proposed topologies include a ring configuration, where the scan chains of each board are each chained; this higher level scan chain would be controlled by a single boundary scan controller. Another proposed topology is a star configuration, the controller would have access to the scan chains of all the boards, but be able to access them in parallel instead of in series. One more proposed topology has a system-level controller's boundary scan connections across the backplane connecting all the boards together. Each board's boundary scan controller interfaces with this bus, and would then provide boundary scan testing to individual boards. No matter the configuration, system-level boundary scan provides benefits in system testability, as testing would be standardized across an entire system, and only a single test sequence would be needed.
This handbook is for guidance only and cannot be cited as a requirement.
This handbook provides guidance on the acquisition of Boundary Scan, or JTAG, technology as part of a larger acquisition of electronic equipment.