UNLIMITED FREE
ACCESS
TO THE WORLD'S BEST IDEAS

SUBMIT
Already a GlobalSpec user? Log in.

This is embarrasing...

An error occurred while processing the form. Please try again in a few minutes.

Customize Your GlobalSpec Experience

Finish!
Privacy Policy

This is embarrasing...

An error occurred while processing the form. Please try again in a few minutes.

NEN-EN-IEC 61523-2

Delay and power calculation standards - Part 2: Pre-layout delay calculation specification for CMOS ASIC libraries

inactive, Most Current
Organization: NEN
Publication Date: 1 September 2002
Status: inactive
Page Count: 48
ICS Code (IT applications in industry): 35.240.50
scope:

Specifies the pre-layout delay calculation method for CMOSI ASIC Librarier which contains cell based primitives and memories to be used during the pre-layout design phase of Logic simulation, Timing verification, and Logic synthesis.

Document History

NEN-EN-IEC 61523-2
September 1, 2002
Delay and power calculation standards - Part 2: Pre-layout delay calculation specification for CMOS ASIC libraries
Specifies the pre-layout delay calculation method for CMOSI ASIC Librarier which contains cell based primitives and memories to be used during the pre-layout design phase of Logic simulation, Timing...
Advertisement