scope:

The scope of this standard is to serve as the data specification language of library elements for design applications used to implement an integrated circuit (IC). The range of abstraction shall include from the register-transfer level (RTL) to the physical level. The language shall model behavior, timing, power, signal integrity, physical abstraction and physical implementation rules of library elements. Library elements for implementation of an IC include sets of predefined components, composed of transistors and interconnect, and sets of predefined rules for the assembly of such components. The design of application-specific ICs (ASICs) in particular relies on the availability of predefined components, called cells. An IC that uses large predefined compound library elements with a standardized functionality, for example, microprocessors as building blocks, is called a system on a chip (SOC). The design of an ASIC or an SOC involves electronic design automation (EDA) tools. These tools assist the designer in the choice and assembly of library elements for creating and implementing the IC and verifying the functionality and performance specification of the IC. In order to create an IC involving several million instances of library elements within a manageable time period counted in weeks or months, the usage of EDA tools is mandatory. A suitable description of library elements for design applications involving EDA tools is required. A key feature is to represent a library element at a level of abstraction that does not reveal the implementation of the library element itself. This is important for the following reasons: - The complexity of the design data itself mandates data reduction. - The complexity of the verification process, i.e., the verification for functional, physical, and electri-cal correctness, mandates that a library element is already characterized and verified by itself. Only the data necessary for creation and verification of the assembled IC is represented in the library. - A library element is considered an intellectual property (IP) of the library provider. Therefore, the purpose of this standard is to provide a modeling language and semantics for the functional, physical, and electrical performance description of technology-specific libraries for cell-based and block-based design. Without a standard, EDA tools would use multiple proprietary and tool-specific library descriptions. The semantics would be defined by tool implementations only, which are subject to change and prone to misinterpretation. Also, there would be redundancy using multiple descriptions for similar library aspects. Therefore, this standard proposes to create a consistent library view suitable as a reference for IC - designers as well as for EDA tool developers and integrators.