VMEbus - Microprocessor system bus for 1 byte to 4 byte data
|Publication Date:||1 August 1994|
|ICS Code (Microprocessor systems):||35.160|
This standard describes a high performance backplane bus for use in microprocessor based sytems. This parallel bus supports single and block transfer cycles on a 32-bit non-multiplexed address and data highway. Transmission is governed by an asynchronous handshaken protocol. The standard supports inter-module interrupts for facilitating quick response to internal and external events. The mechanics of the boards and chassis are based on IEC Publication 297: Dimensions of Panels and Racks. The bus allocation provides for multiprocessor architectures.