scope:

This PAS is applicable to device embedded substrates fabricated by embedding discrete active and passive electronic devices into an inner layer of a substrate with electric connections by vias, conductor plating, conductive paste, and printing. The device embedded substrate may be used as a substrate to mount SMDs to form electronic circuits, as conductor and insulator layers may be formed after embedding electronic devices.

The purpose of this PAS is to obtain common understanding in design, fabrication and use of device embedded substrates in the industry.

This PAS describes the substrate embedding devices including but not limited to module, integrated passive device (IPD), microelectrochemical systems (MEMS), discrete component formed in the fabrication process of the electronic wiring board, and sheet form component. Figure 1 shows examples of device embedding in the fabrication process of the device embedded substrate. Active and passive devices are connected to each other by interlayer vias and/or conductor patterns. Insulating layers are formed using insulating materials with vias for the connection of inside conductor patterns to the conductor patterns formed on the surface(s) of the substrate. Figure 2 shows the substrate with connections using pads, and Figure 3 shows the board using via connections.

The insulating layer includes rigid and flexible insulating resins such as phenol resin, epoxy resin, polyimide resin and modified polyimide resin, which are reinforced with glass cloth, aramid cloth or paper; and resins without reinforcement. Interconnections to the input and output terminals to the embedded device and the surface conductor pattern include conventional interconnection of the terminals of the embedded device to an interconnecting land for SMD, and formation of terminals on the surface of an embedded device by copper plating or vias using conductive paste.

This PAS does not specify the fabrication process of device embedded substrates, via diameter/via land diameter, conductor width/conductor spacing nor conductor line density.