scope:

This standard defines the IEEE 1076.1 language, a hardware description language for the description and the simulation of analog, digital, and mixed-signal systems. The language, also informally known as VHDL-AMS, is built on the IEEE Std 1076-1993 (VHDL) langauge, and extends it to provide capabilities of writing and simulating analog and mixed-signal models.

This document contains the complete reference of the IEEE 1076.1 VHDL language, including the unchanged portions of the base language and the extensions. Formally, IEEE Std 1076.1-1999 defines the extensions only, and portions of text marked with change bars are either exclusively part of IEEE Std 1076.1-1999, or define changes compared to IEEE Std 1076-1993. Portions of text not marked with change bars are identical in this document and in IEEE Std 1076-1993.

The primary audience of this document are implementors of tools supporting the language and advanced users of the language. The document is not intended to provide any introductory or tutorial information. It rather provides formal definitions of language elements and language constructs.

The IEEE 1076.1 language is a superset of the IEEE 1076 language (VHDL). As such, any legal IEEE Std 1076-1993 model is a legal IEEE Std 1076.1-1999 model, and any IEEE 1076.1 tool must provide the same simulation results as obtained with an IEEE 1076 tool. IEEE Std 1076-1993 and IEEE Std 1076.1-1999 will remain separate standards. This means that when IEEE Std 1076-1993 is revised, IEEE Std 1076.1-1993 will not be automatically revised accordingly. A separate effort will be required to keep both standards synchronized and to avoid inconsistencies.