scope:

The document addresses the necessary interaction between IP design with top level design, foundries, and electronic design automation (EDA) vendors. Based on the key parameters and the categorization and applications of typical IP blocks, the essential rules are discussed. Aspects of EDA design system to facilitate integration of IP blocks is addressed, as well as the need for ESD characterization data.

Purpose

This document is intended to highlight the ESD-related issues relevant to intellectual property (IP) selection, IP on-chip usage, and IP integration verification. It addresses best practices which are consolidated between IP providers and IP users. Latch-up rules are only addressed as far as they are related to integration of ESD protection elements.