JEDEC - JESD82-521
DDR5 DATA BUFFER DEFINITION (DDR5DB01)
| Organization: | JEDEC |
| Publication Date: | 1 December 2021 |
| Status: | active |
| Page Count: | 256 |
scope:
This standard defines standard specifications for features and functionality, DC & AC interface parameters and test loading for definition of the DDR5 data buffer for driving DQ and DQS nets on DDR5 LRDIMM applications.
The purpose is to provide a standard for the DDR5DB01 (see Note) logic device, for uniformity, multiplicity of sources, elimination of confusion, ease of device specification, and ease of use.
NOTE: The designation DDR5DB01 refers to the part designation of a series of commercial logic parts common in the industry. This designation is normally preceded by a series of manufacturer specific characters to make up a complete part designation.
This document uses DDR5DB01, Data Buffer, DB or Buffer interchangeably throughout for the DDR5DB01 device naming.
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