scope:

This standard defines a defect coverage accounting method based on simulation models for defects observed within integrated circuits (ICs). The portion of all possible defects that are detected or "covered", by tests of analog and mixed-signal circuits depends, in practice, on many factors (detectability, defect characteristics, detection threshold margin, measurement resolution, operating point, test patterns, etc.), which this standard considers as it defines how to report coverage.

This standard focuses on defects in analog functions. In this context, "defect" is an unintended physical change in a circuit and an "analog function" means a function that has input, internal, or output signals with meaningful values in a defined continuous range. The function has at least one parametric performance that is sufficiently non-deterministic that its test has upper and/or lower limits (the limits may be real numbers or quantized digital equivalents).

This standard considers redundancy, since most analog circuits have redundancy and defect tolerance, intentional or not. This standard does not consider combinations of variations that could result in a circuit failing to meet all its specifications - that is the subject of Monte Carlo simulations during design for yield and multi-parameter analog defect modeling.

The defects considered here are applicable to purely digital circuits too, though typically a simplified fault model (stuck-at, for instance) is utilized for digital functions. Thus, this standard assumes the topic of stuck at fault coverage accounting is addressed for digital circuits by IEEE1804 "Standard for Fault Accounting and Coverage Reporting to Digital Modules."

Purpose

The primary purpose of this standard is to allow people to communicate information about defect coverage in a way that allows assessment of test and circuit quality as well as prediction of important metrics (simulation time, DfT circuit area, test time, test escapes, etc.). Given a circuit description and a test pattern, this standard defines how to enumerate the universe of defects, determine which defects are detected by the test pattern, and report the coverage results.

By defining analog test coverage, this standard is useful for several other purposes.

First, this standard guides efficient simulation of defects to ensure that the defect models achieve a desirable trade-off between cost-effective simulation times and accurate modeling of behavior seen in real circuits.

Second, this standard facilitates estimation of test escape rates (historically measured in defective parts per million -- DPPM) to facilitate trade-offs between cost of test, time to market, and quality. The portion of all potential defects that tests must detect in a circuit will depend on the likelihood of the defects occurring, the consequences of undetected defects in the intended application for the IC, and the likelihood that a defect that occurs has a significant consequence.

Third, this standard facilitates improvements in design for test (DfT) and test generation methods. Many DfT and test techniques, including built-in self-test (BIST), have been developed which, despite cost advantages, are not used in practice because their impact on defect coverage is questioned due to the lack of a well-understood and silicon-corroborated analog defect model. By allowing reliable comparisons of DfT and test techniques, this standard facilitates automation and quality improvements.