scope:

The SSA-PH2 standard (ANSI NCITS 307-1997) defines a physical layer that supports the SSA transport layer 2 (ANSI NCITS 308-1997), and any protocols supported by SSA-TL2 (ANSI NCITS 308-1997).

The goals of SSA-PH2 (ANSI NCITS 307-1997) are:

a) extending the cable distance;

b) copper cable operation at 40 MB/s;

c) full duplex operation to achieve an aggregate 80 MB/s between two ports; and

d) other capabilities that fit within the scope of SSA-PH2 (ANSI NCITS 307-1997) that may be proposed during the development phase by the participants in the project.

This document defines the SSA physical layer 2 (ANSI NCITS 308-1997) of the Serial Storage Architecture (SSA). SSA defines a serial interface hierarchy to be used for purposes within its distance and performance characteristics, including but not limited to storage subsystems. This standard is intended to be used with an upper layer protocol [e.g., SCSI-2 Protocol (ANSI X3.294-1996) or SCSI-3 Protocol (ANSI NCITS 309-1997)] and a transport layer [e.g., SSA Transport Layer 2 (ANSI NCITS 308-1997)].

A major goal of the SSA-PH2 standard (ANSI NCITS 307-1997) is to define a physical layer acceptable to device vendors, looking for an evolution from parallel SCSI or SSA-PH1 (ANSI X3.293-1996), and systems designers looking for opportunities to more fully exploit the capabilities inherent to a serial bus.

SSA-PH2 characteristics

This standard defines the physical medium (e.g., encoding, modulation, clocking, line drivers/receivers, connectors, and cables).

The essential characteristics of SSA-PH2 (ANSI NCITS 307-1997) include:

a) links using copper Cable Assemblies have been demonstrated to operate at 40 MB/s up to 20 m with on-chip CMOS drivers;

b) support for optical transducers that allow longer distance connections;

c) the link makes optimum use of the physical medium by using full-duplex communication to avoid arbitration overhead and turn-around delay;

d) full duplex communication achieves an aggregate 80 MB/s bandwidth (40 MB/s in each direction) between two ports;

e) the cables and connectors are physically compatible with small form factor devices;

f) device connector capable of mating with both backplanes and cables;

g) an electrically balanced design that reduces EMI and crosstalk; and

h) a measurement scheme focusing on interoperability at separable connectors without requiring any internal physical access.