JEDEC - JESD238A
High Bandwidth Memory DRAM (HBM3)
active, Most Current
| Organization: | JEDEC |
| Publication Date: | 1 January 2023 |
| Status: | active |
| Page Count: | 270 |
scope:
The HBM3 DRAM is tightly coupled to the host compute die with a distributed interface. The interface is divided into independent channels. Each channel is completely independent of one another. Channels are not necessarily synchronous to each other. The HBM3 DRAM uses a wide-interface architecture to achieve high-speed, low power operation. Each channel interface maintains a 64 bit data bus operating at double data rate (DDR).
Document History
JESD238A
January 1, 2023
High Bandwidth Memory DRAM (HBM3)
The HBM3 DRAM is tightly coupled to the host compute die with a distributed interface. The interface is divided into independent channels. Each channel is completely independent of one another....