JEDEC - JESD317
Compute Express Link (CXL™) Memory Module Reference Base Standard
| Organization: | JEDEC |
| Publication Date: | 1 March 2023 |
| Status: | active |
| Page Count: | 18 |
scope:
This standard defines the specifications of interface parameters, signaling protocols, environmental requirements, packaging, and other features as reference for specific target implementations of CXL™-attached memory modules.
The purpose is to provide certain reference base targets for CXL™-attached memory modules to enable system design simplification, multiplicity of sources, elimination of confusion, ease of device specification, and ease of use.
Further module design detail may be later found in annexes that comply with this base specification and as associated with the specific base reference modules defined herein.
Unless otherwise noted in the document, device operation is not guaranteed.
JEDEC's CXL™ Memory Module (CMM) Reference Standard leverages and references specific external and JEDEC internal standards:
• PCI Express® (PCIe) Base Specification
• PCI Express® (PCIe) Card Electromechanical Specification
• Compute Express Link Consortium: CXL™ Specification
• SNIA SFF-TA-1002, Card Edge multilane protocol agnostic connector specification
•SNIA SFF-TA-1006 Enterprise and Datacenter 1U Short Device Form Factor available
• SNIA SFF-TA-1008 Enterprise and Datacenter Form Factor
• SNIA SFF-TA-1009 Enterprise and Datacenter Standard Pin and Signal Specification
• SNIA SFF-TA-1023 Thermal Characterization Specification for EDSFF Devices
• JESD405-1 CXL™ Module Label Standard
Module Reference Standard
This standard encompasses a variety of requirements, many of which exist in the industry independently. In most cases, these external specifications are referenced directly without modification. In other cases, this standard provides specific implementations or restrictions on these standards for the intended application.
Document History