scope:

This standard provides the definition of the language syntax and semantics for the IEEE Std 1800™ SystemVerilog language, which is a unified hardware design, specification, and verification language. The standard includes support for behavioral, register transfer level (RTL), and gate-level hardware descriptions; testbench, coverage, assertion, object-oriented, and constrained random constructs; and also provides application programming interfaces (APIs) to foreign programming languages.

Purpose

This standard develops the IEEE Std 1800 SystemVerilog language in order to meet the increasing usage of the language in specification, design, and verification of hardware. This revision corrects errors and clarifies aspects of the language definition in IEEE Std 1800-2017.¹ This revision also provides enhanced features that ease design, improve verification, and enhance cross-language interactions.

¹ Information on references can be found in Clause 2.