scope:

The following labels shall be applied to all DDR5 memory modules to fully describe the key attributes of the module. The label can be in the form of a stick-on label, silk screened onto the assembly, or marked using an alternate customer-readable format. A readable point size should be used, and the information may be printed in one or more rows on the label. Hyphens may be dropped when lines are split, or when font changes sufficiently separate fields. Unused letters in each field, such as ggg, are to be omitted when not needed.

Hybrid modules appear to the system with a "base module type" compatible interface. For example, an NVDIMM-N may be constructed with an RDIMM-style interface or an LRDIMM-style interface. What specific functions the module provides are described in an "Hybrid Media Type" field ('n'), essentially a functional overlay on the base module type.

Terminology:

Rank or Package Rank: Collection of SDRAMs on a DIMM sharing a common chip select or copy of a chip select. Chip selects may be sourced by the host controller or by a redriver device such as registering clock driver.

Logical Rank: 3DS stacked DDR5 SDRAMs decode which internal die is selected by decoding chip identifiers (CIDs) in the command. Each package rank, therefore, may contain multiple logical ranks per package rank, increasing module capacity.

Channel: Addresses, clocks, data and associated signals that span the width of the DIMM interface from and to the host controller. For CAMM2s, a module may support one or two channels; in this context, the term channel refers to the organization of the related sub-channel logic at the host controller, i.e., one or two full host channels are connected to one CAMM2.

Sub-channel: The data across the width of the DDR5 standard DIMMs is divided into two independent sub-channels, each with half the data width of the full DDR5 channel. For example, an RDIMM with 80 data bits of width is internally divided into two sub-channels of 40 bits each (32 data bits and 8 ECC bits). For LPDDR5/5X CAMM2s, each LPDDR5 channel is divided into 4 sub-channels, each 16 bits wide. ECC is not supported.

Though technically a CAMM2 (compression attached memory module) is not a DIMM (dual in-line memory module), for the sake of documentation simplicity, a CAMM2 will be considered a kind of DIMM except when it is necessary to draw a distinction.

Example 1: DDR5 MRDIMM 2Rx8

In this example, the data width of each DDR5 component is 8 bits, arranged as two ranks which are multiplexed through MDB devices to provide a 40-bit word on each sub-channel.

Example 2: LPDDR5/5X CAMM2 2 Channel 1Rx16

In this example, the data width of each LPDDR5/5X component is 32 bits, however, they are organized with separate chip selects for separate x16 data buses internally. This configuration therefore is referred to as "1Rx16", matching the component configuration, and consistent with the definition of "rank" as the data word width associated with each chip select. The sub-channels, however, are explicitly called out such that each 64 bit channel is still comprised of four x16 sub-channels, A through D.

Example 3: DDR5 CAMM2 1 Channel 4Rx8

Single channel versus dual channel CAMM2s are distinguished by the module type field m; for example, G refers to a single channel DDR5 CAMM2, and H refers to a dual channel DDR5 CAMM2.

Example 4: LPDDR5/5X CAMM2 2 Channel 4Rx16

The quad rank LPDDR CAMM2 uses LPDDR5/5X packages with multiple die sharing data lines but using independent chip selects. These designs may have the same module type (field m) and be differentiated by the LPDDR DRAM type installed; the type of device installed is defined in field hee.