UNLIMITED FREE ACCESS TO THE WORLD'S BEST IDEAS

close
Already an Engineering360 user? Log in.

This is embarrasing...

An error occurred while processing the form. Please try again in a few minutes.

Customize Your Engineering360 Experience

close
Privacy Policy

This is embarrasing...

An error occurred while processing the form. Please try again in a few minutes.

JEDEC JEP 162

System Level ESD Part II: Implementation of Effective ESD Robust Designs

active, Most Current
Buy Now
Organization: JEDEC
Publication Date: 1 January 2013
Status: active
Page Count: 140
scope:

This white paper consolidates industry-wide knowledge and experience on the tools and methods used to address failures of printed circuit boards (PCBs) which occur as a result of IEC 61000-4-2 system-level ESD stressing. These include both hard and soft failures, but more emphasis is placed on soft failures from all the observed and anticipated failures and failure scenarios. The methodology is a consistent characterization approach which applies to both IC interfaces and discrete PCB components.

Document History

JEDEC JEP 162
January 1, 2013
System Level ESD Part II: Implementation of Effective ESD Robust Designs
This white paper consolidates industry-wide knowledge and experience on the tools and methods used to address failures of printed circuit boards (PCBs) which occur as a result of IEC 61000-4-2...

References

Advertisement