UNLIMITED FREE
ACCESS TO THE WORLD'S BEST IDEAS

SUBMIT
Already a GlobalSpec user? Log in.

This is embarrasing...

An error occurred while processing the form. Please try again in a few minutes.

Customize Your GlobalSpec Experience

Select Your Free Newsletters

Industry Newsletters

Select Your Free Product Alerts

Finish!
Privacy Policy

This is embarrasing...

An error occurred while processing the form. Please try again in a few minutes.

DLA - DSCC-VID-V62/11605 REV A

MICROCIRCUIT, DIGITAL, NONVOLATILE MEMORY, DUAL 1024-POSITION DIGITAL POTENTIOMETER, MONOLITHIC SILICON

inactive
Organization: DLA
Publication Date: 12 March 2013
Status: inactive
Page Count: 13
scope:

This drawing documents the general requirements of a high performance non volatile memory, dual 1024-position digital potentiometer microcircuit, with an operating temperature range of -40°C to +125°C.

Document History

DSCC-VID-V62/11605 REV B
May 7, 2018
MICROCIRCUIT, DIGITAL, NONVOLATILE MEMORY, DUAL 1024-POSITION DIGITAL POTENTIOMETER, MONOLITHIC SILICON
This drawing documents the general requirements of a high performance non volatile memory, dual 1024-position digital potentiometer microcircuit, with an operating temperature range of -40°C to...
DSCC-VID-V62/11605 REV A
March 12, 2013
MICROCIRCUIT, DIGITAL, NONVOLATILE MEMORY, DUAL 1024-POSITION DIGITAL POTENTIOMETER, MONOLITHIC SILICON
This drawing documents the general requirements of a high performance non volatile memory, dual 1024-position digital potentiometer microcircuit, with an operating temperature range of -40°C to...
DSCC-VID-V62/11605
December 14, 2010
MICROCIRCUIT, DIGITAL, NONVOLATILE MEMORY, DUAL 1024-POSITION DIGITAL POTENTIOMETER, MONOLITHIC SILICON
This drawing documents the general requirements of a high performance non volatile memory, dual 1024-position digital potentiometer microcircuit, with an operating temperature range of -40ºC to...

References

This document references:
JEP95 BOOK 1 - Book One Registered and Standard Outlines for Solid State and Related Products
Published by JEDEC on March 1, 1997
PREFACE This Publication contains those solid state product outlines and other associated drawings that have been registered and assigned a JEDEC designation and are printed on white paper. Product...
This document references:
JEDEC JESD 22-A117 - Electrically Erasable Programmable ROM (EEPROM) Program / Erase Endurance and Data Retention Stress Test
Published by JEDEC on November 1, 2018
This standard specifies the procedural requirements for performing valid endurance, retention and crosstemperature tests based on a qualification specification. Endurance and retention qualification...
This document references:
JEDEC JESD 51-2 - Integrated Circuits Thermal Test Method Environmental Conditions - Natural Convection (Still Air)
Published by JEDEC on January 1, 2008
This document outlines the environmental conditions necessary to ensure accuracy and repeatability for a standard junction-to-ambient thermal resistance measurement in natural convection.
Advertisement