Documentation on design automation subjects – The Bird’s-eye View of Design Languages (BVDL)
|Publication Date:||1 August 2013|
|ICS Code (Industrial automation systems):||25.040|
The BVDL originally aims to make full use of planning and decision-making on EDA standardization activities for a technical expert as well as a manager in JEITA. It facilitates the understanding of the various design languages to show their positioning and features. Also it provides easy overviews of each design language for a newcomer to the EDA standards community and/or for a designer as a user of an EDA design ecosystem. Especially for a design language developer that aims to directly join design language development and voting for standardization, it provides metrics to check for duplication among similar languages, consistency to develop the design ecosystem and future challenges for design languages.
EDA standards provide a mechanism to define common semantics for electronic design ecosystems among various design tools depicted in Figure 1. The state-of-the-art standards are classified into hardware description languages, hardware verification languages, electronic system level design languages, library formats, design constrain formats, interface formats with manufacturing and testing, design data exchange formats, data models and application procedure interfaces (API), etc. Therefore they are generally called standard design languages in a narrow sense. The semiconductor industry has been facing new design complexity barriers and is today facing unprecedented complexities brought by the convergence of product features in terms of silicon process technology, system technology, high gate count and embedded software incorporation. This new design complexity requires integrated EDA solutions and at the same time impacts design ecosystem and standard design languages as well. So a new design language development or new features enhancement to an existing design language is needed. As a result tens of design languages, which might be classified into de jure standard language, de facto standard language, forum standard language and common language used in some community, are developed, enhanced or actually used in the industries, academia and communities world-wide.
This technical report describes features for existing design languages, as well as for enhancing and newly developing design languages belonging to the defined design processes of System on a chip (SoC) which ranges from system level design, SoC design implementation and verification, IP block creation and analog block design down to interface data preparation for manufacturing. These simplified design processes might not become obsolete despite the remarkable speed of the evolution of electronic design automation and seem easier to understand for a non-EDA expert.