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NPFC - MIL-M-38510/343

MICROCIRCUITS, DIGITAL, BIPOLAR, ADVANCED SCHOTTKY TTL, BINARY COUNTERS, MONOLITHIC SILICON

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Organization: NPFC
Publication Date: 21 September 1989
Status: inactive
Page Count: 48
scope:

This specification covers the detail requirements for monolithic silicon, bipolar, Advanced Schottky TTL, binary counter microcircuits. Two product assurance classes and a choice of case outlines and lead finishes are provided and are reflected in the complete Part or Identifying Number (PIN) (see 6.7).

The device types shall be as follows:

Device type Circuit 01 Synchronous 4-bit binary counter (asynchronous master reset) 02 Synchronous 4-bit binary counter (synchronous reset) 03 Synchronous 4-bit up/down binary counter (with mode control) 04 Synchronous 4-bit up/down binary counter (asynchronous master reset)

The device class shall be the product assurance level as defined in MIL-M-38510.

The case outline shall be designated as follows:

Letter Case outline (see MIL-M-38510, appendix C) E D-2 (16-lead, .840" × .310" × .200"), dual-in-line package F F-5 (16-lead, .440" × .285" × .085"), flat package X C-2A (20 terminal, .358" × .358" × .075"), square chip carrier package 2 C-2 (20 terminal, .358" × .358" × .100"), square chip carrier package

Beneficial comments (recommendations, additions, deletions) and any pertinent data which may be of use in improving this document should be addressed to: Rome Air Development Center (RBE-2), Griffiss AFB, NY 13441-5700, by using the self-addressed Standardization Document Improvement Proposal (DD Form 1426) appearing at the end of this document or by letter.

Supply voltage range - - - - - - - - - - - - - - - - −0.5 V dc to +7.0 V dc Input voltage range - - - - - - - - - - - - - - - - −1.2 V dc at −18 mA to +7.0 V dc Storage temperature range - - - - - - - - - - - - - −65°C to +150°C Maximum power dissipation (PD)1/: Device types 01, 02, 03, 04- - - - - - - - - - - - 303 mW Lead temperature (Soldering, 10 seconds) - - - - - - +300°C Thermal resistance, junction-to-case (θJC): Cases E, F, X, 2 - - - - - - - - - - - - - - - - - - See MIL-M-38510, appendix C Junction temperature (TJ) 2/ - - - - - - - - - - - - - +175°C

Supply voltage (VCC)- - - - - - - - - - - - - - - - 4.5 V dc minimum to 5.5 V dc maximum Minimum high level input voltage (VIH)- - - - - - - 2.0 V dc Maximum low level input voltage (VIL) - - - - - - - 0.8 V dc Normalized fanout (each output) 3/: Low level - - - - - - - - - - - - - - - - - - - - - 33 maximum High level- - - - - - - - - - - - - - - - - - - - - 50 maximum Case operating temperature range (TC) - - - - - - - −55°C to +125°C Width of clock pulse, high ([P bar][E bar] = High) Device types 01, 02 - - - - - - - - - - - - - - - - 9.0 ns minimum Width of clock pulse, high ([P bar][E bar] = Low) Device types 01, 02- - - - - - - - - - - - - - - - 7.0 ns minimum Width of clock pulse, low ([P bar][E bar] = High) Device types 01, 02 - - - - - - - - - - - - - - - - 8.0 ns minimum Width of clock pulse, low ([P bar][E bar] = Low) Device types 01, 02 - - - - - - - - - - - - - - - - 9.0 ns minimum Width of master reset pulse, low ([M bar][R bar] = low) Device type 01- - - - - - - - - - - - - - - - - - - 9.5 ns minimum Width of [P bar][L bar] pulse low: Device type 03- - - - - - - - - - - - - - - - - - - 8.5 ns minimum Width of [P bar][L bar] pulse low: Device type 04- - - - - - - - - - - - - - - - - - - 7.5 ns minimum Width of clock pulse low. Device type 03- - - - - - - - - - - - - - - - - - - 7.0 ns minimum Width of CPU or CPD pulse low Device type 04- - - - - - - - - - - - - - - - - - - 7.0 ns minimum Width of master reset pulse, high ([M bar][R bar] = high) Device type 04- - - - - - - - - - - - - - - - - - - 6.0 ns minimum Width of CPU or CPD. pulse, low (change of direction) Device type 04- - - - - - - - - - - - - - - - - - - 12.0 ns minimum Setup. time Pn high to clock pulse Device types 01, 02 - - - - - - - - - - - - - - - - 5.5 ns minimum Setup time Pn low to clock pulse Device types 01, 02 - - - - - - - - - - - - - - - - 5.5 ns minimum Setup time [P bar][E bar] or [S bar][R bar] high to clock pulse Device types 01, 02 - - - - - - - - - - - - - - - - 13.5 ns minimum Setup time [P bar][E bar] or [S bar][R bar] low to clock pulse Device types 01, 02 - - - - - - - - - - - - - - - - 10.5 ns minimum

Setup time CEP or CET high to clock pulse Device types 01, 02 - - - - - - - - - - - - - - - - 13.0 ns minimum Setup time CEP or CET low to clock pulse Device types 01, 02 - - - - - - - - - - - - - - - - 7.5 ns minimum Setup time [U bar]/D high to clock pulse Device type 03- - - - - - - - - - - - - - - - - - - 12.0 ns minimum Setup time [U bar]/D low to clock pulse Device type 03- - - - - - - - - - - - - - - - - - - 12.0 ns minimum Setup time Pn high to [P bar][L bar] Device types 03, 04 - - - - - - - - - - - - - - - - 6.0 ns minimum Setup time Pn low to [P bar][L bar] Device types 03, 04 - - - - - - - - - - - - - - - - 6.0 ns minimum Setup time [C bar][E bar] low to clock pulse Device type 03- - - - - - - - - - - - - - - - - - - 10.5 ns minimum Hold time Pn high to clock pulse Device types 01, 02 - - - - - - - - - - - - - - - - 2.5 ns minimum Hold time Pn low to clock pulse Device types 01, 02 - - - - - - - - - - - - - - - - 2.5 ns minimum Hold time [P bar][E bar] or [S bar][R bar] high to clock pulse Device types 01, 02 - - - - - - - - - - - - - - - - 2.0 ns minimum Hold time [P bar][E bar] or [S bar][R bar] low to clock pulse Device types 01, 02 - - - - - - - - - - - - - - - - 0.0 ns minimum Hold time CEP or CET high to clock pulse Device types 01, 02 - - - - - - - - - - - - - - - - 2.0 ns minimum Hold time CEP or CET low to clock pulse Device types 01, 02 - - - - - - - - - - - - - - - - 2.0 ns minimum Hold time Pn low to [P bar][L bar] Device types 03, 04 - - - - - - - - - - - - - - - - 2.0 ns minimum Hold time [U bar]/D high to clock pulse Device type 03- - - - - - - - - - - - - - - - - - - 0.0 ns minimum Hold time [U bar]/D low to clock pulse Device type 03- - - - - - - - - - - - - - - - - - - 0.0 ns minimum Hold time [C bar][E bar] low to clock pulse Device type 03- - - - - - - - - - - - - - - - - - - 0.0 ns minimum Recovery time master reset to clock pulse Device type 01- - - - - - - - - - - - - - - - - - - 6.0 ns minimum Recovery time [P bar][L bar] to clock pulse Device type 03- - - - - - - - - - - - - - - - - - - 7.5 ns minimum Recovery time master reset to CPU or CPD Device type 04- - - - - - - - - - - - - - - - - - - 4.5 ns minimum Recovery time [P bar][L bar] to CPU or CPD Device type 04- - - - - - - - - - - - - - - - - - - - 8.0 ns minimum

intended Use:

Microcircuits conforming to this specification are intended for original equipment design applications and logistic support of existing equipment.

Document History

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April 20, 1994
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August 11, 1993
MICROCIRCUITS, DIGITAL, BIPOLAR, ADVANCED SCHOTTKY TTL, BINARY COUNTERS, MONOLITHIC SILICON
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October 7, 1992
MICROCIRCUITS, DIGITAL, BIPOLAR, ADVANCED SCHOTTKY TTL, BINARY COUNTERS, MONOLITHIC SILICON
A description is not available for this item.
MIL-M-38510/343
September 21, 1989
MICROCIRCUITS, DIGITAL, BIPOLAR, ADVANCED SCHOTTKY TTL, BINARY COUNTERS, MONOLITHIC SILICON
This specification covers the detail requirements for monolithic silicon, bipolar, Advanced Schottky TTL, binary counter microcircuits. Two product assurance classes and a choice of case outlines and...
July 16, 1986
MICROCIRCUITS, DIGITAL, BIPOLAR, ADVANCED SCHOTTKY TTL, BINARY COUNTERS, MONOLITHIC SILICON
A description is not available for this item.
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