DLA - SMD-5962-96534
MICROCIRCUIT, DIGITAL, RADIATION HARDENED, ADVANCED CMOS, DUAL D FLIP-FLOP WITH CLEAR AND PRESET, MONOLITHIC SILICON
| Organization: | DLA |
| Publication Date: | 13 May 1996 |
| Status: | inactive |
| Page Count: | 16 |
scope:
This drawing documents two product assurance class levels consisting of high reliability (device classes Q and M) and space application (device class V). A choice of case outlines and lead finishes are available and are reflected in the Part or Identifying Number (PIN). When available, a choice of Radiation Hardness Assurance (RHA) levels are reflected in the PIN.
The PIN is as shown in the following example:
Device classes Q and V RHA marked devices meet the MIL-PRF-38535 specified RHA levels and are marked with the appropriate RHA designator. Device class M RHA marked devices meet the MIL-PRF-38535, appendix A specified RHA levels and are marked with the appropriate RHA designator. A dash (-) indicates a non-RHA device.
The device type(s) identify the circuit function as follows:
Device type Generic number Circuit function 01 54ACS74 Radiation hardened, dual D flip-flop with clear and preset
The device class designator is a single letter identifying the product assurance level as follows:
Device class Device requirements documentation M Vendor self-certification to the requirements for MIL-STD-883 compliant, non-JAN class level B microcircuits in accordance with MIL-PRF-38535, appendix A Q or V Certification and qualification to MIL-PRF-38535
The case outline(s) are as designated in MIL-STD-1835 and as follows:
Outline letter Descriptive designator Terminals Package style C GDIP1-T14 or CDIP2-T14 14 Dual-in-line X CDFP3-F14 14 Flat pack
The lead finish is as specified in MIL-PRF-38535 for device classes Q and V or MIL-PRF-38535, appendix A for device class M.
Supply voltage range (VDD) . . . . . . . . . . . . . . . . . −0.3 V dc to +7.0 v dc DC input voltage range(VIN) . . . . . . . . . . . . . . . . −0.3 V dc to VDD + 0.3 V dc DC output voltage range (VOUT) . . . . . . . . . . . . . . . −0.3 V dc to VDD + 0.3 V dc DC input current, any one input (IIN) . . . . . . . . . . . ±10 mA Latch-up immunity current (ILU) . . . . . . . . . . . . . . ±150 mA Storage temperature range (TSIG) . . . . . . . . . . . . . . −65°C to +150°C Lead temperature (soldering, 5 seconds) . . . . . . . . . . +300°C Thermal resistance, junction-to-case (ΘJC) . . . . . . . . . See MIL-STD-1835 Junction temperature (TJ) . . . . . . . . . . . . . . . . . +175°C Maximum package power dissipation (PD) . . . . . . . . . . . 1.0 W
Supply voltage range (VDD) . . . . . . . . . . . . . . . . . +4.5 V dc to +5.5 V dc Input voltage range (VIN) . . . . . . . . . . . . . . . . . +0.0 V dc to VDD Output voltage range (VOUT) . . . . . . . . . . . . . . . . +0.0 V dc to VDD Case operating temperature range (TC) . . . . . . . . . . . −55°C to +125°C Maximum input rise and fall time at VDD = 4.5 V (tr, tf) . . 1 ns/V 4/
Total dose . . . . . . . . . . . . . . . . . . . . . . . . . > 1 × 106 Rads (Si) Single event phenomenon (SEP) effective linear energy threshold (LET) no upsets (see 4.4.4.4) . . > 80 MeV/(mg/cm2) Dose rate upset (20 ns pulse) . . . . . . . . . . . . . . . > 1 × 109 Rads (Si)/s Latch-up . . . . . . . . . . . . . . . . . . . . . . . . . . None Dose rate survivability . . . . . . . . . . . . . . . . . . > 1 × 1012 Rads (Si)/s
intended Use:
Microcircuits conforming to this drawing are intended for use for Government microcircuit applications (original equipment), design applications, and logistics purposes.
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