DS/EN 61523-2
Delay and power calculation standards - Part 2: Pre-layout delay calculation specification for CMOS ASIC libraries
inactive, Most Current
| Organization: | DS |
| Publication Date: | 23 September 2002 |
| Status: | inactive |
| Page Count: | 45 |
| ICS Code (IT applications in industry): | 35.240.50 |
scope:
This standard specifies the pre-layout delay calculation method for CMOS1 ASIC Libraries which contains cell based primitives and memories to be used during the pre-layout design phase of Logic simulation, Timing verification, and Logic synthesis. The delay calculation method addressed in this standard consists of 1) Estimation of wire capacitance and 2) Delay calculation method based on table look-up.
Document History
DS/EN 61523-2
September 23, 2002
Delay and power calculation standards - Part 2: Pre-layout delay calculation specification for CMOS ASIC libraries
This standard specifies the pre-layout delay calculation method for CMOS1 ASIC Libraries which contains cell based primitives and memories to be used during the pre-layout design phase of Logic...
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