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DLA - SMD-5962-97523

MICROCIRCUIT, MEMORY, DIGITAL, CMOS, PROGRAMMABLE LOGIC ARRAY, MONOLITHIC SILICON

inactive
Organization: DLA
Publication Date: 31 July 1997
Status: inactive
Page Count: 43
scope:

This drawing documents two product assurance class levels consisting of high reliability (device classes Q and M) and space application (device class V). A choice of case outlines and lead finishes are available and are reflected in the Part or Identifying Number (PIN). When available, a choice of Radiation Hardness Assurance (RHA) levels are reflected in the PIN.

The PIN shall be as shown in the following example:

Device classes Q and V RHA marked devices meet the MIL-PRF-38535 specified RHA levels and are marked with the appropriate RHA designator. Device class M RHA marked devices meet the MIL-PRF-38535, appendix A specified RHA levels and are marked with the appropriate RHA designator. A dash (-) indicates a non-RHA device.

The device type(s) shall identify the circuit function as follows:

Device type Generic number Circuit function Access time 01 4010E-4 10000 gate programmable array 4 ns

The device class designator shall be a single letter identifying the product assurance level as follows:

Device class Device requirements documentation M Vendor self-certification to the requirements for MIL-STD-883 compliant, non- JAN class level B microcircuits in accordance with MIL-PRF-38535, appendix A Q or V Certification and qualification to MIL-PRF-38535

The case outline(s) shall be as designated in MIL-STD-1835 and as follows:

Outline letter Descriptive designator Terminals Package style X CMGA8-P191 191 1/ Pin grid array package Y see figure 1 196 Quad flat package Z see figure 1 196 Quad flat package

The lead finish is as specified in MIL-PRF-38535 for device classes Q and V or MIL-PRF-38535, appendix A for device class M.

Supply voltage range to ground potential (V CC) ...... −0.5 V dc to +7.0 V dc DC input voltage range ............................ −0.5 V dc to VCC +0.5 V dc Voltage applied to three-state output(V IS) .......... −0.5 V dc to VCC +0.5 V dc Maximum power ........................................ 2.0 W Thermal resistance, junction-to-case (θ JC): Case outline X .................................... See MIL-STD-1835 Case outline Y and Z .............................. 20°C/W 3/ Junction temperature (T J) ........................... +150°C 4/ Lead temperature (soldering, 10 seconds) ............ +260°C Storage temperature range .......................... −65°C to +150°C

Case operating temperature Range(T C) ................ −55°C to +125°C Supply voltage relative to ground(V CC) .............. +4.5 V dc minimum to +5.5 V dc maximum Ground voltage (GND) ................................. 0 V dc

Fault coverage measurement of manufacturing logic tests (MIL-STD-883, test method 5012) ...... XX percent 6/

intended Use:

Microcircuits conforming to this drawing are intended for use for Government microcircuit applications (original equipment), design application, and logistics purposes.

Microcircuits... View More

Document History

June 19, 2017
MICROCIRCUIT, MEMORY, DIGITAL, CMOS, PROGRAMMABLE LOGIC ARRAY, MONOLITHIC SILICON
This drawing documents two product assurance class levels consisting of high reliability (device class Q) and space application (device class V). A choice of case outlines and lead finishes are...
August 5, 2008
MICROCIRCUIT, MEMORY, DIGITAL, CMOS, PROGRAMMABLE LOGIC ARRAY, MONOLITHIC SILICON
This drawing documents two product assurance class levels consisting of high reliability (device classes Q and M) and space application (device class V). A choice of case outlines and lead finishes...
May 10, 2002
MICROCIRCUIT, MEMORY, DIGITAL, CMOS, PROGRAMMABLE LOGIC ARRAY, MONOLITHIC SILICON
A description is not available for this item.
SMD-5962-97523
July 31, 1997
MICROCIRCUIT, MEMORY, DIGITAL, CMOS, PROGRAMMABLE LOGIC ARRAY, MONOLITHIC SILICON
This drawing documents two product assurance class levels consisting of high reliability (device classes Q and M) and space application (device class V). A choice of case outlines and lead finishes...
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