scope:

This specification covers the detail requirements for monolithic silicon, PROM microcircuits which employ thin film nichrome (NiCr) resistors, platinum-silicide, tungsten (W), titanium-tungsten (TiW) or zapped vertical emitter as the fusible link or programming element. Two product assurance classes and a choice of case outlines and lead finishes are provided for each type and are reflected in the part number. A special test requirement is included in this specification to screen against devices which may contain excess moisture in the package materials or internal atmosphere (see freeze-out test of 4.2d).

The part number shall be in accordance with MIL-M-38510.

The device type shall be as follows:

Device type Circuit Access times (ns) 01 2048 words/8 bits per word PROM with uncommitted 100, 50 collector 02 2048 words/8 bits per word PROM with active pullup 100, 50 and a third high-impedance state output 03 2048 words/8 bits per word PROM with uncommitted 55, 30 collector 04 2048 words/8 bits per word PROM with active pullup 55, 30 and a third high-impedance state output 05 4096 words/4 bits per word PROM with active pullup 80, 40 and a third high-impedance state output

The device class shall be the product assurance level as defined in MIL-M-38510.

The case outline shall be designated as follows:

Letter Case outline (see MIL-M-38510, appendix C) J D-3 (24-lead, ½" × 1-¼"), dual-in-line package K F-6 (24-lead, ⅜" × ⅝"), flat package R $ D-8 (20-lead, ¼" × 1-1/16"), dual-in-line package L D-9 (24-lead, ¼" × 1-¼"), dual-in-line package 3 C-4 (28-terminal, .450" × .450"), square chip carrier package

Beneficial comments (recommendations, additions, deletions) and any pertinent data which may be of use in improving this document should be addressed to: Rome Air Development Center (RBE-2), Griffiss AFB, NY 13441, by using the self-addressed Standardizetion Document Improvement Proposal (DD Form 1426) appearing at the end of this document or by letter.

Supply voltage range - - - - - - - - - - - - - −0.5 V dc to +7.0 V dc Input voltage range - - - - - - - - - - - - - - −1.5 V dc at −10 mA to +5.5 V dc Storage temperature range - - - - - - - - - - - −65°C to +150°C Lead temperature (soldering, 10 seconds)- - - - +300°C Thermal resistance, junction-to-case (θ_JC): 1/ Cases J, L, and R - - - - - - - - - - - - - - 40°C/W maximum Case K - - - - - - - - - - - - - - - - - - - 60°C/W maximum Case 3 - - - - - - - - - - - - - - - - - - - 0.08°C/W maximum 2/ Output voltage range - - - - - - - - - - - - - −0.5 V dc to +V_CC Output sink current - - - - - - - - - - - - - - 100 mA Maximum power dissipation (P_D) 3/ - - - - - - - 1.02 W Maximum junction temperature (T_J) 4/ - - - - - +175°C

Supply voltage - - - - - - - - - - - - 4.5 V dc minimum to 5.5 V dc maximum Minimum high-level input voltage (V_IH)- 2.0 V dc Maximum low-level input voltage (V_IL) - 0.8 V dc Normalized fanout (each output) - - - - 8 mA 5/ Case operating temperature range (T_C) - −55°C to +125°C

intended Use: