scope:

This document establishes the requirements and test procedures for the procurement of an electronic interface receiver module.

The following electrical parameters reflect the −55° to 100°C end-of-life limits from table II.

Name Receiver, interface Family Digital Key code JDK Size 1A Weight 35 grams maximum Failure rate Class I 0.278 failures/10⁶ hours maximum Class II 2.395 failures/10⁶ hours maximum Environment Classes I and II as specified in MIL-STD-1389 Supply voltage 5.0 Vdc ±10% 15.0 Vdc ±10% −5.0 Vdc ±5% Maximum power dissipation 2.23 W (all outputs in low level) 2.0 W (all outputs in high level) Input voltage Low level 1.8 V maximum High level 3.2 V minimum Input current Low level (V_IL = −2.0 V) 4.7 mA maximum High level (V_IH = 15.0 V) 50 µA maximum

Beneficial comments (recommendations, additions, deletions) and any pertinent data which may be of use in improving this document should be addressed to: Commander, Naval Electronic Systems Command, ATTN: ELEX 5043, Department of the Navy, Washington, DC 20360 by using the self-addressed Standardization Document Improvement Proposal (DD Form 1426) appearing at the end of this document or by letter.

Output voltage Low level 0.4 V maximum High level 2.4 V minimum, V_CC maximum Output current Low level (V_OL = 0.4 V) 12.8 mA maximum High level (V_OH = 2.4 V) 320 µA minimum Propagation delay time t_PHL 10 ns minimum, 37 ns maximum t_PLH 10 ns minimum, 32 ns maximum

This module contains 18 receiver circuits as illustrated on figure 1. It is intended for use as a receiver when transmitting logic level signals from chassis to chassis within an equipment cabinet. When flat cable is used for interconnection, the length shall be less than 7 feet, and the driver and receiver shall be located adjacent to the ends of the cable. A dedicated driver shall be used to drive the interface receiver. A dedicated driver is defined as a circuit that drives no other circuits, either on its own module, or on another module except the interface receiver module. The driver circuit must be capable of driving at low level a −16 mA minimum at 0.4 V and at high level a +1.0 mA minimum at 2.4 V.

Each interface receiver shall have the following input and output relationship for positive logic:

Paralleling of outputs is not permissible.

The module has the following crosstalk relationships.

When connected in the worst case mode of operation (all outputs but one switching simultaneously), the JDK module could exhibit substantial crosstalk. When a quiet output is a low level, there may be as much as an 820 mV positive going spike.

The crosstalk on any output pin is nearly directly proportional to the number of switching outputs. For every switching output in group A (circuits 1-4), the noise induced on a low level quiet output in group A is as much as 110 mV. For every switching output outside group A, the noise induced on a low level quiet output in group A is as much as 35 mV. The preceding relationship applies to group B (circuits 5-8), group C (circuits 9-11), group D (circuits 12-15), and group E (circuits 16-18).