DLA - DSCC-VID-V62/03626
MICROCIRCUIT, DIGITAL-LINEAR, 3.3 V DUAL UNIVERSAL ASYNCHRONOUS RECEIVER/TRANSMITTER WITH 64 BYTE FIFO, MONOLITHIC SILICON
inactive
| Organization: | DLA |
| Publication Date: | 20 March 2003 |
| Status: | inactive |
| Page Count: | 20 |
Document History
September 26, 2022
MICROCIRCUIT, DIGITAL-LINEAR, 3.3 V DUAL UNIVERSAL ASYNCHRONOUS RECEIVER/TRANSMITTER WITH 64 BYTE FIFO, MONOLITHIC SILICON
Scope.
This drawing documents the general requirements of a high performance 3.3 V dual universal asynchronous receiver / transmitter with 64-byte FIFO microcircuit, with an operating temperature...
DSCC-VID-V62/03626
March 20, 2003
MICROCIRCUIT, DIGITAL-LINEAR, 3.3 V DUAL UNIVERSAL ASYNCHRONOUS RECEIVER/TRANSMITTER WITH 64 BYTE FIFO, MONOLITHIC SILICON
A description is not available for this item.