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DLA - SMD-5962-85154 REV A

MICROCIRCUIT, DIGITAL, HIGH-SPEED CMOS, DUAL J-K FLIP-FLOP WITH RESET, MONOLITHIC SILICON

inactive
Organization: DLA
Publication Date: 20 December 1986
Status: inactive
Page Count: 14
scope:

This drawing describes device requirements for class B microcircuits in accordance with 1.2.1 of MIL-STD-883, "Provisions for the use of MIL-STD-883 in conjunction with compliant non-JAN devices".

The complete part number shall be as shown in the following example:

The device type shall identify the circuit function as follows:

Device type Generic number Circuit function 01 54HC107 Dual J-K flip-flop with reset

The case outlines shall be as designated in appendix C of MIL-M-38510, and as follows:

Outline letter Case outline C D-1 (14-lead, ¼" × ¾"), dual-in-line package 2 C-2 (20 terminal, .350" × .350"), square chip carrier package

Supply voltage range - - - - - - - - - - - - - - - - - −0.5 V dc to +7.0 V dc DC input voltage - - - - - - - - - - - - - - - - - - - −0.5 V dc to VCC +0.5 V dc DC output voltage- - - - - - - - - - - - - - - - - - - −0.5 V dc to VCC +0.5 V dc. Clamp diode current- - - - - - - - - - - - - - - - - - ±20 mA DC output current (per pin)- - - - - - - - - - - - - - ±25 mA DC VCC or GND current (per pin)- - - - - - - - - - - - ±50 mA Storage temperature range- - - - - - - - - - - - - - - −65°C to +150°C Maximum power dissipation (PD) - - - - - - - - - - - - 500 mW 2/ Lead temperature (soldering, 10 seconds) - - - - - - - 260°C Thermal resistance, junction-to-case (θJC) 3/: Case C - - - - - - - - - - - - - - - - - - - - - - - See MIL-M-38510, appendix C Case 2 - - - - - - - - - - - - - - - - - - - - - - - 60°C/W Junction temperature (TJ)- - - - - - - - - - - - - - - 175°C

Supply voltage - - - - - - - - - - - - - - - - - - - - +2.0 V dc to +6.0 V dc Case operating temperature range - - - - - - - - - - - −55°C to +125°C Input rise or fall time: VCC = 2.0 V- - - - - - - - - - - - - - - - - - - - - 0 to 1,000 ns VCC = 4.5 V- - - - - - - - - - - - - - - - - - - - - 0 to 500 ns VCC = 6.0 V- - - - - - - - - - - - - - - - - - - - - 0 to 400 ns

Minimum setup time, J or K to clock (ts): Case at 25°C, VCC = 2.0 V - - - - - - - - - - - - - - - 100 ns VCC = 4.5 V - - - - - - - - - - - - - - - 20 ns VCC = 6.0 V - - - - - - - - - - - - - - - 17 ns Case at −55°C/+125°C, VCC = 2.0 V - - - - - - - - - - - 150 ns VCC = 4.5 V - - - - - - - - - - - 30 ns VCC = 6.0 V - - - - - - - - - - - 26 ns Minimum recovery time, reset inactive to clock (trec): Case at 25°C, VCC = 2.0 V - - - - - - - - - - - - - - - 100 ns VCC = 4.5 V - - - - - - - - - - - - - - - 20 ns VCC = 6.0 V - - - - - - - - - - - - - - - 17 ns Case at −55°C/+125°C VCC = 2.0 V - - - - - - - - - - - 150 ns VCC = 4.5 V - - - - - - - - - - - 30 ns VCC = 6.0 V - - - - - - - - - - - 26 ns Minimum clock pulse width (tw): Case at 25°C, VCC = 2.0 V - - - - - - - - - - - - - - - 90 ns VCC = 4.5 V - - - - - - - - - - - - - - - 18 ns VCC = 6.0 V - - - - - - - - - - - - - - - 15 ns Case at −55°C/+125°C, VCC = 2.0 V - - - - - - - - - - - 135 ns VCC = 4.5 V - - - - - - - - - - - 27 ns VCC = 6.0 V - - - - - - - - - - - 23 ns Minimum reset pulse width (tw): Case at 25°C, VCC = 2.0 V - - - - - - - - - - - - - - - 100 ns VCC = 4.5 V - - - - - - - - - - - - - - - 20 ns VCC = 6.0 V - - - - - - - - - - - - - - - 17 ns Case at −55°C/+125°C, VCC = 2.0 V - - - - - - - - - - - 150 ns VCC = 4.5 V - - - - - - - - - - - 30 ns VCC = 6.0 V - - - - - - - - - - - 26 ns Minimum hold time, clock to J or K(tH): Case at 25°C, VCC = 2.0 V - - - - - - - - - - - - - - - 25 ns VCC = 4.5 V - - - - - - - - - - - - - - - 5 ns VCC = 6.0 V - - - - - - - - - - - - - - - 5 ns Case at −55°C/+125°C, VCC = 2.0 V - - - - - - - - - - 40 ns VCC = 4.5 V - - - - - - - - - - - 8 ns VCC = 6.0 V - - - - - - - - - - - 7 ns Maximum frequency (fmax): Case at 25°C, VCC = 2.0 V - - - - - - - - - - - - - - - 5.4 MHz VCC = 4.5 V - - - - - - - - - - - - - - - 27 MHz VCC = 6.0 V - - - - - - - - - - - - - - - 32 MHz Case at −55°C/+125°C, VCC = 2.0 V - - - - - - - - - - - 3.6 MHz VCC = 4.5 V - - - - - - - - - - - 18 MHz VCC = 6.0 V - - - - - - - - - - - 21 MHz

intended Use:

Microcircuits conforming to this drawing are intended for use when military specifications do not exist and qualified military devices that will perform the required function are not available for... View More

Document History

October 26, 2020
MICROCIRCUIT, DIGITAL, HIGH-SPEED CMOS, DUAL J-K FLIP-FLOP WITH RESET, MONOLITHIC SILICON
Scope. This drawing describes device requirements for MIL-STD-883 compliant, non-JAN class level B microcircuits in accordance with MIL-PRF-38535, appendix A.
August 27, 2013
MICROCIRCUIT, DIGITAL, HIGH-SPEED CMOS, DUAL J-K FLIP-FLOP WITH RESET, MONOLITHIC SILICON
Microcircuits conforming to this drawing are intended for use for Government microcircuit applications (original equipment), design applications, and logistics purposes.
November 28, 2007
MICROCIRCUIT, DIGITAL, HIGH-SPEED CMOS, DUAL J-K FLIP-FLOP WITH RESET, MONOLITHIC SILICON
Microcircuits conforming to this drawing are intended for use for Government microcircuit applications (original equipment), design applications, and logistics purposes.
October 18, 2001
MICROCIRCUIT, DIGITAL, HIGH-SPEED CMOS, DUAL J-K FLIP-FLOP WITH RESET, MONOLITHIC SILICON
A description is not available for this item.
SMD-5962-85154 REV A
December 20, 1986
MICROCIRCUIT, DIGITAL, HIGH-SPEED CMOS, DUAL J-K FLIP-FLOP WITH RESET, MONOLITHIC SILICON
This drawing describes device requirements for class B microcircuits in accordance with 1.2.1 of MIL-STD-883, "Provisions for the use of MIL-STD-883 in conjunction with compliant non-JAN devices"....
July 14, 1986
MICROCIRCUIT, DIGITAL, HIGH-SPEED CMOS, DUAL J-K FLIP-FLOP WITH RESET, MONOLITHIC SILICON
A description is not available for this item.
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