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NPFC - MIL-M-38510/657

MICROCIRCUITS, DIGITAL, HIGH SPEED CMOS, BUFFER GATES, MONOLITHIC SILICON

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Organization: NPFC
Publication Date: 30 September 1986
Status: inactive
Page Count: 110
scope:

This specification covers the detail requirements for monolithic silicon, high speed, CMOS logic microcircuits without/with TTL input voltage level compatibility. Two product assurance classes and a choice of case outlines and lead finishes are provided and are reflected in the complete part number.

The part number shall be in accordance with MIL-M-38510, and as specified herein.

The device type shall be as follows:

Device type Circuit 01/51 Hex inverter 02/52 Hex inverter schmitt trigger 03/53 Inverting octal three-state buffer 04/54 Octal three-state buffer 05/55 Octal three-state buffer 06 Hex bus driver, gated enable inputs for X-Y coincident bus control (three-state) 07 Hex inverter bus driver, gated enable inputs for X-Y coincident bus control (three-state) 08 Hex Bus driver, 4-line and 2-line enable inputs (three-state) 09 Hex inverter bus driver, 4-line and 2-line enable inputs (three-state) 10/60 Octal inverter bus driver (three-state) 11/61 Octal non-inverting bus driver (three-state)

The device class shall be the product assurance level as defined in MIL-M-38510.

The case outlines shall be designated as follows:

Outline letter Case outline (see MIL-M-38510, appendix C) C D-1 (14-lead, ¼" × ¾"), dual-in-line package E D-2 (16-lead, ¼" × ⅞"), dual-in-line package R D-8 (20-lead, ¼" × 1 1/16"), dual-in-line package D F-2 (14-lead, ¼" × ⅜"'), flat package F F-5 (16-lead, ¼" × ⅜"), flat package S F-9 (20-lead, ¼" × ½"), flat package 2 C-2 (20-terminal, .350" × .350"), square chip carrier package

Beneficial comments (recommendations, additions, deletions) and any pertinent data which may be of use in improving this document should be addressed to: Rome Air Development Center (RBE-2), Griffiss AFB, NY 13441, by using the self-addressed Standardization Document Improvement Proposal (DD Form 1426) appearing at the end of this document or by letter.

Supply voltage (VCC) - - - - - - - - - - - - - - −0.5 V dc +7.0 V dc DC input voltage (VIN) - - - - - - - - - - - - - −0.5 V dc to VCC +0.5 V dc DC output voltage (VOUT) - - - - - - - - - - - - −0.5 V dC to VCC +0.5 V dc Clamp diode current IIK, IOK) - - - - - - - - - ±20 mA DC output current per pin (IOUT) 01/51, 02/52 - ±25 mA (03, 04, 05, 06, 07, 08, 09 10, 11)- - - - - - ±35 mA DC VCC or GND current per pin (IOC) 01/51, 02/52 ±50 mA (53, 54, 55, 60, 61) - - - - - - - - - - - - ±70 mA Storage temperature range (TSTG) - - - - - - - - −65°C to +150°C Maximum power dissipation (PD) - - - - - - - - - 300 mW Lead temperature (soldering, 10 seconds) - - - - +300°C Thermal resistance, Junction-to-case (θJC): All except C-2 - - - - - - - - - - - - - - - - See MIL-M-38510, appendix C C-2 - - - - - - - - - - - - - - - - - - - - - 60°C/W Junction temperature (TJ) - - - - - - - - - - - +175°C

Device types 01, 03 through 11: Input low (VIL) maximum voltage - - - - - 0.3 V at VCC = 2 V 0.9 V at VCC = 4.5 V 1.2 V at VCC = 6 V Input high (VIH) minimum voltage- - - - - 1.5 V at VCC = 2 V 3.15 V at VCC = 4.5 V 4.2 V at VCC = 6 V Device type 02: Input low (VIL) maximum voltage - - - - - 1.0 V at VCC = 2 V 2.45 V at VCC = 4.5 V 3.2 V at VCC = 6 V Input high (VIH) minimum voltage- - - - - 0.7 V at VCC = 2 V 1.55 V at VCC = 4.5 V 2.1 V at VCC = 6 V Device types 51, 53, 54, 55, 60, 61: Input low (VIL) maximum voltage - - - - - 0.8 V at VCC = 4.5-5.5 V Input high (VIH) minimum voltage - - - - - 2.0 V at VCC = 4.5-5.5 V Device type 52: Input low (VIL) maximum voltage - - - - - - 0.6 V at VCC = 5.5 V Input high (VIH) minimum voltage- - - - - - 1.9 V at VCC = 4.5 V Device types 01 through 11: Supply voltage (VCC) - - - - - - - 2 V dc to 6 V dc Output voltage - - - - - - - - - - 0 V dc to VCC. Operating temperature- - - - - - - −55°C to +125°C Input rise and fall times (tr, tf) maximum: Except 02 VCC = 2 V 1000 ns VCC = 4.5 V 500 ns VCC = 6 V 400 ns Device types 51, 52, 53, 54, 55, 60, 61: Supply voltage (VCC)- - - - - - - - - - - - - - - - 4.5 V dc to 5.5 V dc Output voltage- - - - - - - - - - - - - - - - - - - 0 V dc to VCC Operating temperature - - - - - - - - - - - - - - - −55°C to +125°C Input rise and fall times (tr, tf) maximum: Except 52 VCC = 4.5 V - 5.5 V 500 ns

intended Use:

Microcircuits conforming to this specification are intended for original equipment design application and logistic support of existing equipment.

Document History

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March 17, 1998
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August 22, 1994
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June 16, 1994
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December 3, 1993
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A description is not available for this item.
December 21, 1992
MICROCIRCUITS, DIGITAL, HIGH SPEED CMOS, BUFFER GATES, MONOLITHIC SILICON
A description is not available for this item.
MIL-M-38510/657
September 30, 1986
MICROCIRCUITS, DIGITAL, HIGH SPEED CMOS, BUFFER GATES, MONOLITHIC SILICON
This specification covers the detail requirements for monolithic silicon, high speed, CMOS logic microcircuits without/with TTL input voltage level compatibility. Two product assurance classes and a...

References

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