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DLA - DESC-DWG-76004 REV E

MICROCIRCUITS, DIGITAL, LOW POWER SCHOTTKY TTL, POSITIVE NAND GATES, MONOLITHIC SILICON

inactive, Most Current
Organization: DLA
Publication Date: 23 January 1986
Status: inactive
Page Count: 9
scope:

This drawing describes the requirements for monolithic silicon, low-power Schottky TTL, positive NAND logic gating microcircuits. This drawing provides for a level of microcircuit quality and reliability assurance for acquisition of microcircuits in accordance with MIL-M-38510.

The complete part number shall be as shown in the following example:

The device type shall identify the circuit function as follows:

Device type Generic number Circuit 01 54LS132 Quadruple, 2-input Schmitt-Trigger positive NAND gates.

The case outlines shall be as designated in MIL-M-38510, appendix C and as follows:

Outline letter Case outline C D-1 (14-lead, ¼″ × ¾″), dual-in-line package D F-2 (14-lead, ¼″ × ⅜″), flat package

Supply voltage range - - - - - - - - - - - - - - - −0.5 V dc to 7.0 V dc Input voltage range- - - - - - - - - - - - - - - - −1.5 V dc at −18 mA to 5.5 V dc Storage temperature range- - - - - - - - - - - - - −65°C to +150°C Maximum power dissipation (PD) 1/- - - - - - - - - 77 mW Lead temperature (soldering, 10 seconds) - - - - - +300°C Thermal resistance, junction-to-case (θJC):- - - - (See MIL-M-38510, appendix C) Junction temperature (TJ)- - - - - - - - - - - - - +175°C

Supply voltage (VCC) - - - - - - - - - - - - - - - 4.5 V dc minimum to 5.5 V dc maximum Minimum high level input voltage (VIH) - - - - - - 1.9 V dc Maximum low level input voltage (VIL)- - - - - - - 0.5 V dc Case operating temperature range (TC)- - - - - - - −55°C to +125°C

intended Use:

Microcircuits conforming to this drawing are intended for use when military specifications do not exist and qualified military devices that will perform the required function are not available for... View More

Document History

DESC-DWG-76004 REV E
January 23, 1986
MICROCIRCUITS, DIGITAL, LOW POWER SCHOTTKY TTL, POSITIVE NAND GATES, MONOLITHIC SILICON
This drawing describes the requirements for monolithic silicon, low-power Schottky TTL, positive NAND logic gating microcircuits. This drawing provides for a level of microcircuit quality and...
September 17, 1985
MICROCIRCUITS, DIGITAL, LOW POWER SCHOTTKY TTL, POSITIVE NAND GATES, MONOLITHIC SILICON
A description is not available for this item.
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