NPFC - MIL-M-38510/291
MICROCIRCUITS, DIGITAL, CMOS 16,384-BIT STATIC RANDOM ACCESS MEMORY (RAM) MONOLITHIC SILICON
| Organization: | NPFC |
| Publication Date: | 12 September 1988 |
| Status: | inactive |
| Page Count: | 89 |
scope:
This specification covers the detail requirements for monolithic silicon, CMOS, 16,384-bit static random access memory microcircuits. Two product assurance classes and a choice of case outlines, lead finishes, and radiation hardness assured (RHA) products are reflected in the complete part number.
The complete part number shall be in accordance with MIL-M-38510.
The device types shall be as shown in the following:
Device type Circuit organization Access time 01 2,048 words/8 bits 150 ns 02 2,048 words/8 bits 210 ns (synchronous) 03 16,384 words/1 bit 85 ns 04 2,048 words/8 bits 90 ns 05 2,048 words/8 bits 200 ns 06 16,384 words/1 bit 45 ns 07 (RHA) 16,384 words/1 bit 150 ns 08 (RHA) 16,384 words/1 bit 175 ns 09 16,384 words/1 bit 70 ns 10 2,048 words/8 bits 70 ns
The device class shall be the product assurance level as defined in MIL-M-38510.
The case outlines shall be designated as follows:
Outline letter Case outline (see MIL-M-38510, appendix C) J D-3 (24-lead, 1.290" × .610" × .225"), dual-in-line package R D-8 (20-lead, 1.060"× .310"× .200"), dual-in-line package X C-12 (32-terminal, .560" × .458" × .120" maximum), leadless chip carrier package Y C-13 (20-terminal, .440" × .306" × .120" maximum), leadless chip carrier package Z F-6A (24-lead, .640" × .420" × .115" maximum) flat package
Radiation hardness levels shall be as defined in MIL-M-38510. Beneficial comments (recommendations, additions, deletions) and any pertinent data which may be of use in improving this document should be addressed to: Rome Air Development Center,RBE-2, Griffiss AFB, NY 13441-5700, by using the self-addressed Standardization Document Improvement Proposal (DD Form 1426) appearing at the end of this document or by letter.
Supply voltage range (VCC-VSS)- - - - - - - - - - −0.3 V dc to +7.0 V dc Input voltage range - - - - - - - - - - - - - - - (VSS −0.3 V) ≤ VI ≤ (VCC +0.3 V) Storage temperature range - - - - - - - - - - - - −65°C to +150°C Maximum dc output current - - - - - - - - - - - - 50 mA Maximum power dissipation (PD)- - - - - - - - - - 1 W Lead temperature (soldering, 5 seconds) - - - - - +270°C Junction temperature (TJ) 1/ - - - +150°C Thermal resistance, junction-to-case (θJC) 2/: Cases J, R, and Z - - - - - - - - - - - - - - - See MIL-M-38510, appendix C Cases X and Y - - - - - - - - - - - - - - - - - 14°C/W
Supply voltages: VCCDR (data retention supply voltage): Device types 01 through 06 and device types 09 and 10 - - - - - - - - - - - - - - - - - 2.0 V dc Device types 07 and 08- - - - - - - - - - - - 3.0 V dc VCC - - - - - - - - - - - - - - - - - - - - - - 4.5 V dc minimum to 5.5 V dc maximum VSS - - - - - - - - - - - - - - - - - - - - - - 0 V dc High level input voltage (VIH) (all inputs): Device types 01, 03 through 06 and device types 09 and 10 - - - - - - - - - - - - - - - VCC −2.3 V to VCC +0.3 V Device type 02- - - - - - - - - - - - - - - - - VCC −2.1 V to VCC +0.3 V Device type 07- - - - - - - - - - - - - - - - - VCC −1.5 V to VCC +0.3 V Device type 08- - - - - - - - - - - - - - - - - 2.3 V to VCC +0.3 V Low level input voltage (VIL) (all inputs): All device types- - - - - - - - - - - - - - - - VSS −0.3 V to +0.8 V Case operating temperature range (TC) - - - - - - −55°C to +125°C
intended Use:
Microcircuits conforming to this specification are intended for original equipment design application and logistic support of existing equipment.
Document History