scope:

This drawing forms a part of a one part - one part number documentation system (see 6.6 herein). Two product assurance classes consisting of military high reliability (device classes Q and M) and space application (device class V), and a choice of case outlines and lead finishes are available and are reflected in the Part or Identifying Number (PIN). Device class M microcircuits represent non-JAN class B microcircuits in accordance with 1.2.1 of MIL-STD-883, "Provisions for the use of MIL-STD-883 in conjunction with compliant non-JAN devices". When available, a choice of Radiation Hardness Assurance (RHA) levels are reflected in the PIN.

The PIN shall be as shown in the following example:

Device class M RHA marked devices shall meet the MIL-I-38535 appendix A specified RHA levels and shall be marked with the appropriate RHA designator. Device classes Q and V RHA marked devices shall meet the MIL-I-38535 specified RHA levels and shall be marked with the appropriate RHA designator. A dash (-) indicates a non-RHA device.

The device type(s) shall identify the circuit function as follows:

Device type Generic number Circuit function 01 54ACTS00 Radiation hardened, quad 2-input NAND gate, TTL compatible input

The device class designator shall be a single letter identifying the product assurance level as follows:

Device class Device requirements documentation M Vendor self-certification to the requirements for non-JAN class B microcircuits in accordance with 1.2.1 of MIL-STD-883 Q or V Certification and qualification to MIL-I-38535

The case outline(s) shall be as designated in MIL-STD-1835 and as follows:

Outline letter Descriptive designator Terminals Package style C GDIP1-T14 or CDIP2-T14 14 Dual-in-Line X CDFP3-Fl4 14 Flat pack

The lead finish shall be as specified in MIL-STD-883 (see 3.1 herein) for class M or MIL-I-38535 for classes Q and V. Finish letter "X" shall not be marked on the microcircuit or its packaging. The "X" designation is for use in specifications when lead finishes A, B, and C are considered acceptable and interchangeable without preference.

Supply voltage range (V_DD): . . . . . . . . . . . . . . . . . . . . −0.3 V dc to +7.0 V dc DC input voltage range any pin (V_IO): . . . . . . . . . . . . . . . −0.3 V dc to V_DD 0.3 V dc DC input current, any one input (I_IN) . . . . . . . . . . . . . . . ±10 mA Latch-up immunity current (I_LU) . . . . . . . . . . . . . . . . . . ±150 mA Storage temperature range (T_STG) . . . . . . . . . . . . . . . . . −65°C to +150°C Lead temperature (soldering, 5 seconds) . . . . . . . . . . . . . . +300°C Thermal resistance, junction-to-case (Θ_JC) . . . . . . . . . . . . See MIL-STD-1835 Junction temperature (T_J) . . . . . . . . . . . . . . . . . . . . . +175°C Maximum package power dissipation (P_D) . . . . . . . . . . . . . . . 1.0 W

Supply voltage range (V_DD) . . . . . . . . . . . . . . . . . . . . . . . +4.5 V dc to +5.5 V dc Input voltage range (V_IN) . . . . . . . . . . . . . . . . . . . . . . . +0.0 V dc to V_DD Output voltage range (V_OUT) . . . . . . . . . . . . . . . . . . . . . . +0.0 V dc to V_DD Maximum low level input voltage (V_IL) . . . . . . . . . . . . . . . . . 0.8 V Maximum Minimum high level input voltage (V_IH) . . . . . . . . . . . . . . . . . 0.5 V_DD Minimum Case operating temperature range (T_C) . . . . . . . . . . . . . . . . . −55°C to +125°C Maximum input rise and fall time at V_DD = 4.5 V (t_r, t_f) . . . . . . . . 1 ns/V 4/

Total dose . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . > 1 × 10⁶ Rads (SI) Single event phenomenon (SEP) effective linear energy threshold (LET) No upsets (see 4.4.4.4) . . . . . . . . . > 80 MeV/(mg/cm²) Dose rate upset (20 ns pulse) . . . . . . . . . . . . . . . . . . . . . > 1 × 10⁹ Rads (SI)/s Latch-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . None Dose rate survivability . . . . . . . . . . . . . . . . . . . . . . . . > 1 × 10¹² Rads (SI)/s

intended Use: