NPFC - MIL-M-38510/261
MICROCIRCUITS, MEMORY, DIGITAL, CMOS 32K X 8-BIT, ELECTRICALLY ERASABLE PROGRAMMABLE READ-ONLY MEMORY (EEPROM), MONOLITHIC SILICON
| Organization: | NPFC |
| Publication Date: | 27 March 1989 |
| Status: | active |
| Page Count: | 34 |
scope:
This specification covers the detail requirements for monolithic silicon, CMOS, 32K words/8-bit, 5.0-volt, electrically erasable programmable read-only memory microcircuits. Two product assurance classes (B and S), a choice of lead finish and three package types are provided for each device and are reflected in the complete part number.
The part number shall be in accordance with MIL-M-38510.
The device types shall be as shown in the following:
Device Circuit Access Write Write Software type organization time speed mode Endurance data protect 01 32K words/8-bit 350 ns 10 ms Byte/page 10,000 cy No 02 32K words/8-bit 300 ns 10 ms Byte/page 10,000 cy No 03 32K words/8-bit 250 ns 10 ms Byte/page 10,000 cy No 04 32K words/8-bit 200 ns 10 ms Byte/page 10,000 cy No 05 32K words/8-bit 150 ns 10 ms Byte/page 10,000 cy No 06 32K words/8-bit 250 ns 10 ms Byte/page 100,000 cy No 07 32K words/8-bit 350 ns 10 ms Byte/page 10,000 cy Yes 08 32K words/8-bit 300 ns 10 ms Byte/page 10,000 cy Yes 09 32K words/8-bit 250 ns 10 ms Byte/page 10,000 cy Yes 10 32K words/8-bit 200 ns 10 ms Byte/page 10,000 cy Yes 11 32K words/8-bit 150 ns 10 ms Byte/page 10,000 cy Yes 12 32K words/8-bit 250 ns 10 ms Byte/page 100,000 cy Yes
The device class shall be the product assurance level as defined in MIL-M-38510.
The case outlines shall be designated in appendix C of MIL-M-38510, and as follows:
Outline letter Case outline U Figure 1 (28-lead, .660" × .560" × .100"), pin grid array X D-10 (28-lead, 1.490" × .610" × .232"), dual-in-line package Y C-12 (32-terminal, .560" × .458" × .120"), rectangular chip carrier package Z F-12 (28-lead, .740" × .420" × .130"), flat package
Beneficial comments (recommendations, additions, deletions) and any pertinent data which may be of use in improving this document should be addressed to: Rome Air Development Center, RBE-2, Griffiss AFB, NY 13441, by using the self-addressed Standardization Document Improvement Proposal (DD Form 1426) appearing at the end of this document or by letter.
All input and output voltages (including VCC) 1/- - −0.5 V dc to +6.0 V dc Voltage for chip clear (Vh)- - - - - - - - - - - - - +15.0 V dc Operating case temperature range - - - - - - - - - - −55°C to +125°C Storage temperature range- - - - - - - - - - - - - - −65°C to +150°C Lead temperature (soldering, 10 seconds) - - - - - - +300°C Thermal resistance, junction-to-case (θJC) - - - - - See MIL-M-38510, appendix C Maximum power dissipation (PD) 2/ - - - - - - - - - 1.0 W Junction temperature (TJ) 3/- - - - - - - - - - - - +175°C Endurance: Device types 01-05 and 07-11 - - - - - - - - - - - 10,000 cycles/byte, minimum Device types 06 and 12 - - - - - - - - - - - - - - 100,000 cycles/byte, minimum Data retention - - - - - - - - - - - - - - - - - - - 10 years, minimum
Supply voltage range (VCC) - - - - - - - - - - - - - +4.5 V dc to +5.5 V dc Case operating temperature range (TC) - - - - - - - - −55°C to +125°C Input voltage, low range (VIL) - - - - - - - - - - - −0.1 V dc to +0.8 V dc Input voltage, high range (VIH) - - - - - - - - - - - +2.0 V dc to VCC+0.3 V dc High level chip erase voltage (Vh) - - - - - - - - - 12 V dc to 13 V dc
intended Use:
Microcircuits conforming to this specification are intended for original equipment design applications and logistic support of existing equipment.
Document History