IPC-SMC-WP-003
Chip Mounting Technology (CMT)
| Organization: | IPC |
| Publication Date: | 1 August 1993 |
| Status: | active |
| Page Count: | 35 |
scope:
INTRODUCTION
The purpose of this paper is to investigate emerging chip attachment methods and define and classify the attachment methods for electronic systems designers and manufacturers today. The industry is on the threshold of the next generation of electronic packaging as the component density limitations of fine pitch technology are approached. Chip Mounting Technology is appearing on the technology horizon as a viable option to higher system densities. The name "Chip Mounting Technology" (CMT) was selected in keeping with the conventions of Through Hole Technology (THT), Surface Mount Technology (SMT), and Fine Pitch Technology (FPT) . Throughout the paper, the terms "chip" and "device" will be used interchangeably to describe the integrated circuit die.
In the past decade, active device packaging has evolved from
Through Hole Technology, with component leads on 2.54mm [.100"]
centers, to Surface Mount Technology with leads on 1.27mm [.050"]
and smaller centers. This has recently been followed by the
evolution of Fine Pitch Technology with component leads on 0.63mm
[.025"] and 0.5mm [.020"] . Through these evolutions the component
package which contains the silicon die, or chip, has decreased in
size while lead counts have increased dramatically. The reduction
in die geometries has been the result of semiconductor technology
improvements, particularly lithogr
We recognize that there are some advanced electronics companies who have been practicing these "new" packaging concepts for years. If it were not for their pioneering efforts, technology would come to a standstill. The objective of this paper is to simply describe, and help bring the results of those innovative packaging efforts into the mainstream of electronic package design and manufacturing.
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