scope:

This document is part of a series of documents describing a technology assessment cycle of submicron CMOS technologies. The series consists of six closely related documents (1, 2, 3, 4, 5) in addition to this one. A documentation of the steps and the objective of the entire technology assessment cycle is the contents of (1). The transistor model which is able to deal with the effects of modern submicron CMOS technologies is presented in (2). Test structurs usable for the extraction of MOS transistor parameters are descibed in (3).