Standard Guide for Analysis of Crystallographic Perfection of Silicon Wafers
|Publication Date:||10 June 1997|
|ICS Code (Semiconducting materials):||29.045|
1.1 This guide covers the determination of the density of crystallographic defects in unpatterned polished and epitaxial silicon wafers. Epitaxial silicon wafers may exhibit dislocations, hillocks, shallow pits or epitaxial stacking faults, while polished wafers may exhibit several forms of crystallographic defects or surface damage. Use of this practice is based upon the application of several referenced standards in a prescribed sequence to reveal and count microscopic defects or structures.
1.2 Materials for which this practice is applicable may be defined by the limitations of the referenced documents.
1.2.1 This practice is suitable for use with epitaxial or polished wafers grown in either  or  direction and doped either p or n-type with resistivity greater than 0.005 Ω-cm.
1.2.2 This practice is suitable for use with epitaxial wafers with layer thickness greater than 0.5 µm.
1.3 This standard does not purport to address all of the safety concerns, if any, associated with its use. It is the responsibility of the user of this standard to establish appropriate safety and health practices and determine the applicability of regulatory limitations prior to use.