JEDEC JESD 82
Definition of CDCV857 PLL Clock Driver for Registered DDR DIMM Applications
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| Organization: | JEDEC |
| Publication Date: | 1 July 2000 |
| Status: | active |
| Page Count: | 17 |
scope:
This specification is a reference for Registered DDR DIMM designers. JESD82 defines the physical, electrical, interface and timing requirements of a 1:10 PLL clock driver for DDR Registered DIMMs from DDR200 to DDR266 as refined in revision C of JEDEC Standard 21-C (JESD21-C). JESD82 was also written to meet the future performance requirements of Registered DIMMs for DDR300 and DDR333.
Document History
JEDEC JESD 82
July 1, 2000
Definition of CDCV857 PLL Clock Driver for Registered DDR DIMM Applications
This specification is a reference for Registered DDR DIMM designers. JESD82 defines the physical, electrical, interface and timing requirements of a 1:10 PLL clock driver for DDR Registered DIMMs...
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